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path: root/llvm/lib/Target/R600/SIInstrInfo.cpp
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* R600 -> AMDGPU renameTom Stellard2015-06-131-2723/+0
| | | | llvm-svn: 239657
* R600/SI: Fix verifier error when producing v_madmk_f32Matt Arsenault2015-04-241-0/+3
| | | | | | Copy the kill flags when swapping the operands. llvm-svn: 235687
* R600/SI: Special case v_mov_b32 as really rematerializableMatt Arsenault2015-04-231-0/+14
| | | | | | | This should be fixed to properly understand all rematerializable instructions while ignoring implicit reads of exec. llvm-svn: 235671
* R600/SI: Improve BFM supportMarek Olsak2015-03-241-0/+1
| | | | llvm-svn: 233077
* R600/SI: Use V_FRACT_F64 for faster 64-bit floor on SIMarek Olsak2015-03-241-0/+20
| | | | | | | Other f64 opcodes not supported on SI can be lowered in a similar way. v2: use complex VOP3 patterns llvm-svn: 233076
* R600/SI: Merge tables for commutingMatt Arsenault2015-03-231-20/+0
| | | | | | | Don't use a separate table for compares anymore, and use the same VOP2_REV class. llvm-svn: 232992
* R600/SI: Allow commuting comparesMatt Arsenault2015-03-231-2/+24
| | | | | | | | | | | | | | | | | This enables very common cases to switch to the smaller encoding. All of the standard LLVM canonicalizations of comparisons are the opposite of what we want. Compares with constants are moved to the RHS, but the first operand can be an inline immediate, literal constant, or SGPR using the 32-bit VOPC encoding. There are additional bad canonicalizations that should also be fixed, such as canonicalizing ge x, k to gt x, (k + 1) if this makes k no longer an inline immediate value. llvm-svn: 232988
* R600/SI: Fix crash in SIInstrInfo::areLoadsFromSameBasePtr()Tom Stellard2015-03-231-2/+10
| | | | | | | This function assumed that SMRD instructions always have immediate offsets, which is not always the case. llvm-svn: 232957
* Remove the need to cache the subtarget in the R600 TargetRegisterInfoEric Christopher2015-03-111-29/+6
| | | | | | classes. llvm-svn: 231954
* R600/SI: Re-order MUBUF operands to match asm strings.Tom Stellard2015-03-101-4/+3
| | | | llvm-svn: 231797
* R600/SI: Move kill flag to second instruction when splitting SMRDTom Stellard2015-03-101-5/+12
| | | | | | | This fixes a machine verifier error in the salu-to-valu.ll, which would have been exposed by a future commit. llvm-svn: 231796
* R600/SI: Add an intrinsic for S_FLBIT_I32 / V_FFBH_I32Marek Olsak2015-03-041-0/+1
| | | | | | Required by OpenGL (ARB_gpu_shader5). llvm-svn: 231259
* Make some non-constant static variables non-static or fully const.Benjamin Kramer2015-03-011-4/+1
| | | | | | Otherwise we have to emit thread-safe initialization for them. NFC. llvm-svn: 230894
* R600/SI: Add slc, glc, and tfe to non-atomic _ADDR64 instructionsTom Stellard2015-02-271-1/+7
| | | | llvm-svn: 230757
* R600/SI: Use v_madmk_f32Matt Arsenault2015-02-211-4/+51
| | | | llvm-svn: 230149
* R600/SI: Try to use v_madak_f32Matt Arsenault2015-02-211-0/+78
| | | | | | | This is a code size optimization when the constant only has one use. llvm-svn: 230148
* R600/SI: Simplify verification of AMDGPU::OPERAND_REG_INLINE_CMarek Olsak2015-02-181-8/+6
| | | | llvm-svn: 229751
* R600/SI: Remove explicit VOP operand checkingMarek Olsak2015-02-181-28/+0
| | | | | | This should be handled by the OperandType checking. llvm-svn: 229750
* R600/SI: Fix brace identationMatt Arsenault2015-02-181-1/+1
| | | | llvm-svn: 229603
* R600/SI: Fix copies from SGPR to VCCMatt Arsenault2015-02-141-5/+10
| | | | | | | This shows up without optimizations when vcc is required to be used. llvm-svn: 229226
* R600/SI: Add hack to copy from a VGPR to VCCMatt Arsenault2015-02-141-0/+10
| | | | | | This hopefully should be fixed when VReg_1 is removed. llvm-svn: 229225
* R600/SI: Allow f64 inline immediates in i64 operandsMatt Arsenault2015-02-131-21/+41
| | | | | | | This requires considering the size of the operand when checking immediate legality. llvm-svn: 229135
* R600/SI: Remove unnecessary check for fpimmMatt Arsenault2015-02-131-1/+1
| | | | llvm-svn: 229034
* R600/SI: Add soffset operand to mubuf addr64 instructionTom Stellard2015-02-111-3/+2
| | | | | | We were previously hard-coding soffset to 0. llvm-svn: 228775
* R600/SI: Fix B64 VALU shifts on VIMarek Olsak2015-02-031-0/+18
| | | | | | | SI only has standard versions. VI only has REV versions. Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 228037
* R600/SI: Don't generate non-existent LSHL, LSHR, ASHR B32 variants on VIMarek Olsak2015-02-031-2/+6
| | | | | | | | | | | | | | | This can happen when a REV instruction is commuted. The trick is not to define the _vi versions of instructions, which has these consequences: - code generation will always fail if a pseudo cannot be lowered (very useful to catch bugs where an unsupported instruction somehow makes it to the printer) - ability to query if a pseudo can be lowered, which is done in commuteOpcode to prevent REV from commuting to non-REV on VI Tested-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 227990
* Reuse a bunch of cached subtargets and remove getSubtarget callsEric Christopher2015-01-301-3/+2
| | | | | | without a Function argument. llvm-svn: 227638
* R600/SI: Add subtarget feature to enable VGPR spilling for all shader typesTom Stellard2015-01-201-11/+3
| | | | | | | This is disabled by default, but can be enabled with the subtarget feature: 'vgpr-spilling' llvm-svn: 226597
* R600/SI: Use external symbols for scratch bufferTom Stellard2015-01-201-2/+2
| | | | | | | | We were passing the scratch buffer address to the shaders via user sgprs, but now we use external symbols and have the driver patch the shader using reloc information. llvm-svn: 226586
* R600/SI: Update SIInstrInfo:verifyInstruction() after r225662Tom Stellard2015-01-201-6/+12
| | | | | | | Now that we have our own custom register operand types, we need to handle them in the verifiier. llvm-svn: 226583
* R600/SI: Use 64-bit encoding by default for opcodes that are VOP3-only on VIMarek Olsak2015-01-151-3/+3
| | | | llvm-svn: 226190
* R600/SI: Don't shrink instructions whose e32 encoding doesn't existMarek Olsak2015-01-151-1/+5
| | | | | | | | v2: modify hasVALU32BitEncoding instead v3: - add pseudoToMCOpcode helper to AMDGPUInstInfo, which is used by both hasVALU32BitEncoding and AMDGPUMCInstLower::lower - report an error if a pseudo can't be lowered llvm-svn: 226188
* R600/SI: Use IMPLICIT_DEF and KILL when failing to spill VGPRsTom Stellard2015-01-141-3/+2
| | | | | | | This helps us avoid 'invalid register class for operand' verifier errors. llvm-svn: 225989
* R600/SI: Spill VGPRs to scratch space for compute shadersTom Stellard2015-01-141-9/+17
| | | | llvm-svn: 225988
* R600/SI: Add pattern for bitcasting fp immediates to integersTom Stellard2015-01-131-18/+14
| | | | | | | | The backend now assumes that all immediates are integers. This allows us to simplify immediate handling code, becasue we no longer need to handle fp and integer immediates differently. llvm-svn: 225844
* R600/SI: Use RegisterOperands to specify which operands can accept immediatesTom Stellard2015-01-121-2/+2
| | | | | | | | | | | | There are some operands which can take either immediates or registers and we were previously using different register class to distinguish between operands that could take immediates and those that could not. This patch switches to using RegisterOperands which should simplify the backend by reducing the number of register classes and also make it easier to implement the assembler. llvm-svn: 225662
* R600/SI: Commute instructions to enable more folding opportunitiesTom Stellard2015-01-071-1/+4
| | | | llvm-svn: 225410
* R600/SI: Remove VReg_32 register classTom Stellard2015-01-071-11/+11
| | | | | | | | | | | Use VGPR_32 register class instead. These two register classes were identical and having separate classes was causing SIInstrInfo::isLegalOperands() to be overly conservative in some cases. This change is necessary to prevent future paches from missing a folding opportunity in fneg-fabs.ll. llvm-svn: 225382
* R600/SI: Add a V_MOV_B64 pseudo instructionTom Stellard2015-01-071-0/+31
| | | | | | | This is used to simplify the SIFoldOperands pass and make it easier to fold immediates. llvm-svn: 225373
* R600/SI: Teach SIFoldOperands to split 64-bit constants when foldingTom Stellard2015-01-071-0/+10
| | | | | | | | | | | | | | | This allows folding of sequences like: s[0:1] = s_mov_b64 4 v_add_i32 v0, s0, v0 v_addc_u32 v1, s1, v1 into v_add_i32 v0, 4, v0 v_add_i32 v1, 0, v1 llvm-svn: 225369
* R600/SI: isLegalOperand() shouldn't check constant bus for SALU instructionsTom Stellard2014-12-191-1/+1
| | | | | | | The constant bus restrictions only apply to VALU instructions. This enables SIFoldOperands to fold immediates into SALU instructions. llvm-svn: 224623
* R600/SI: Fix f64 inline immediatesMatt Arsenault2014-12-171-12/+26
| | | | llvm-svn: 224458
* R600/SI: Handle physical registers in getOpRegClassMatt Arsenault2014-12-111-2/+7
| | | | llvm-svn: 224079
* R600/SI: Don't verify constant bus usage of flag opsMatt Arsenault2014-12-111-2/+10
| | | | | | | | | | | | This was checking if pseudo-operands like the source modifiers were using the constant bus, which happens to work because the values these all can be happen to be valid inline immediates. This fixes a later commit which starts checking the register class of the operands. llvm-svn: 224078
* R600/SI: Set 20-bit immediate byte offset for SMRD on VIMarek Olsak2014-12-071-13/+23
| | | | llvm-svn: 223614
* R600/SI: Update instruction conversions for VIMarek Olsak2014-12-071-0/+27
| | | | | | | | | There are 3 changes: - Convert 32-bit S_LSHL/LSHR/ASHR to their V_*REV variants for VI - Lower RSQ_CLAMP for VI - Don't generate MIN/MAX_LEGACY on VI llvm-svn: 223604
* R600/SI: Set the ATC bit on all resource descriptors for the HSA runtimeTom Stellard2014-12-021-4/+14
| | | | llvm-svn: 223125
* R600/SI: Various instruction format bit test cleanupsMatt Arsenault2014-12-011-52/+0
| | | | | | | | | | | - Fix missing SALU format bits - Remove unused isSALUInstr - Add isVALU - Switch isDS to use a bit like the others - Move SIInstrInfo::is* functions to header - Reorder so they are approximately sorted by type (SALU, VALU, memory) llvm-svn: 223038
* R600/SI: Add an s_mov_b32 to patterns which use the M0RegClassTom Stellard2014-11-211-20/+0
| | | | | | | We need to use a s_mov_b32 rather than a copy, so that CSE will eliminate redundant moves to the m0 register. llvm-svn: 222584
* R600/SI: Make SIInstrInfo::isOperandLegal() more strictTom Stellard2014-11-191-1/+10
| | | | | | | | | | | | A register operand that has a common sub-class with its instruction's defined register class is not always legal. For example, SReg_32 and M0Reg both have a common sub-class, but we can't use an SReg_32 in instructions that expect a M0Reg. This prevents the llvm.SI.sendmsg.ll test from failing when the fold operand pass is added. llvm-svn: 222368
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