diff options
| author | Tom Stellard <thomas.stellard@amd.com> | 2014-08-01 00:32:28 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-08-01 00:32:28 +0000 |
| commit | 86d12ebdbd33c0d04f4ecd74003a51abb55d488f (patch) | |
| tree | 42fbe6faf19617c410a8832f9b0f835ab20e36ef /llvm/lib/Target/R600/SIInstrInfo.cpp | |
| parent | 05fb383d2b867b8cfcbcbd0cd28cd1d67bcae998 (diff) | |
| download | bcm5719-llvm-86d12ebdbd33c0d04f4ecd74003a51abb55d488f.tar.gz bcm5719-llvm-86d12ebdbd33c0d04f4ecd74003a51abb55d488f.zip | |
R600/SI: Fix incorrect commute operation in shrink instructions pass
We were commuting the instruction by still shrinking it using the
original opcode.
NOTE: This is a candidate for the 3.5 branch.
llvm-svn: 214463
Diffstat (limited to 'llvm/lib/Target/R600/SIInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/SIInstrInfo.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/SIInstrInfo.cpp b/llvm/lib/Target/R600/SIInstrInfo.cpp index 0249ad07208..fc395ee4919 100644 --- a/llvm/lib/Target/R600/SIInstrInfo.cpp +++ b/llvm/lib/Target/R600/SIInstrInfo.cpp @@ -668,6 +668,10 @@ bool SIInstrInfo::isImmOperandLegal(const MachineInstr *MI, unsigned OpNo, return RI.regClassCanUseImmediate(OpInfo.RegClass); } +bool SIInstrInfo::hasVALU32BitEncoding(unsigned Opcode) const { + return AMDGPU::getVOPe32(Opcode) != -1; +} + bool SIInstrInfo::verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const { uint16_t Opcode = MI->getOpcode(); |
