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path: root/llvm/lib/Target/R600/SIISelLowering.cpp
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* R600 -> AMDGPU renameTom Stellard2015-06-131-2241/+0
* R600: Switch to using generic min / max nodes.Matt Arsenault2015-06-091-8/+12
* R600/SI: Reimplement isLegalAddressingModeMatt Arsenault2015-06-041-30/+66
* R600/SI: Fix some cases for load / store of halfMatt Arsenault2015-06-041-3/+29
* R600/SI: Don't hardcode pointer typeMatt Arsenault2015-06-011-4/+5
* Add address space argument to isLegalAddressingModeMatt Arsenault2015-06-011-1/+1
* R600/SI: Remove explicit m0 operand from v_interp instructionsTom Stellard2015-05-121-1/+22
* R600/SI: Remove explicit m0 operand from s_sendmsgTom Stellard2015-05-121-1/+24
* Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes"Sergey Dmitrouk2015-04-281-42/+48
* Revert "[DebugInfo] Add debug locations to constant SD nodes"Daniel Jasper2015-04-281-48/+42
* [DebugInfo] Add debug locations to constant SD nodesSergey Dmitrouk2015-04-281-42/+48
* R600: Make FMIN/MAXNUM legal on all asicsJan Vesely2015-04-121-2/+0
* R600/SI: Initial support for assembler and inline assemblyTom Stellard2015-04-081-0/+35
* R600/SI: Use V_FRACT_F64 for faster 64-bit floor on SIMarek Olsak2015-03-241-1/+1
* R600/SI: Expand fract to floor, then only select V_FRACT on CIMarek Olsak2015-03-241-0/+6
* R600/SI: don't try min3/max3/med3 with f64Tom Stellard2015-03-161-0/+1
* Remove the need to cache the subtarget in the R600 TargetRegisterInfoEric Christopher2015-03-111-4/+30
* Make constant arrays that are passed to functions as const.Benjamin Kramer2015-03-071-7/+3
* Remove an argument-less call to getSubtargetImpl from TargetLoweringBase.Eric Christopher2015-02-261-1/+1
* R600/SI: Remove isel mubuf legalizationTom Stellard2015-02-241-124/+0
* CodeGen: convert CCState interface to using ArrayRefsTim Northover2015-02-211-2/+2
* R600/SI: Remove v_sub_f64 pseudoMatt Arsenault2015-02-201-13/+2
* R600: Use new fmad node.Matt Arsenault2015-02-201-29/+20
* Prefer SmallVector::append/insert over push_back loops.Benjamin Kramer2015-02-171-14/+6
* AArch64: Safely handle the incoming sret call argument.Andrew Trick2015-02-161-3/+3
* R600/SI: Implement correct f64 fdivMatt Arsenault2015-02-141-1/+65
* R600/SI: Allow f64 inline immediates in i64 operandsMatt Arsenault2015-02-131-4/+2
* R600/SI: Add soffset operand to mubuf addr64 instructionTom Stellard2015-02-111-0/+1
* R600/SI: Expand misaligned 16-bit memory accessesTom Stellard2015-02-041-0/+5
* R600/SI: Make more store operations legalTom Stellard2015-02-041-9/+0
* R600/SI: 64-bit and larger memory access must be at least 4-byte alignedTom Stellard2015-02-021-4/+4
* Reuse a bunch of cached subtargets and remove getSubtarget callsEric Christopher2015-01-301-34/+30
* R600/SI: Implement enableAggressiveFMAFusionMatt Arsenault2015-01-291-1/+30
* R600/SI: Add subtarget feature for if f32 fma is fastMatt Arsenault2015-01-291-1/+1
* R600/SI: Add subtarget feature to enable VGPR spilling for all shader typesTom Stellard2015-01-201-0/+6
* R600/SI: Fix bad code with unaligned byte vector loadsMatt Arsenault2015-01-141-3/+16
* Implement new way of expanding extloads.Matt Arsenault2015-01-141-6/+9
* R600/SI: Add pattern for bitcasting fp immediates to integersTom Stellard2015-01-131-5/+5
* R600/SI: Remove redundant setting expand on f64 vectorsMatt Arsenault2015-01-121-7/+0
* R600/SI: Use RegisterOperands to specify which operands can accept immediatesTom Stellard2015-01-121-4/+2
* R600/SI: Remove SIISelLowering::legalizeOperands()Tom Stellard2015-01-081-173/+1
* [SelectionDAG] Allow targets to specify legality of extloads' resultAhmed Bougacha2015-01-081-17/+24
* R600/SI: Remove VReg_32 register classTom Stellard2015-01-071-6/+6
* R600/SI: Add combine for isinfinite patternMatt Arsenault2015-01-061-0/+56
* R600/SI: Pattern match isinf to v_cmp_class instructionsMatt Arsenault2015-01-061-0/+33
* R600/SI: Add basic DAG combines for fp_classMatt Arsenault2015-01-061-1/+48
* Enable (sext x) == C --> x == (trunc C) combineMatt Arsenault2014-12-211-21/+2
* R600/SI: Fix f64 inline immediatesMatt Arsenault2014-12-171-22/+21
* R600/SI: Don't promote f32 select to i32Matt Arsenault2014-12-121-2/+0
* R600/SI: Use unordered equal instructionsMatt Arsenault2014-12-111-4/+0
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