bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Expand)	Author	Age	Files	Lines
*	R600 -> AMDGPU rename	Tom Stellard	2015-06-13	1	-303/+0
*	[CodeGen] ArrayRef'ize cond/pred in various TII APIs. NFC.	Ahmed Bougacha	2015-06-11	1	-4/+6
*	Remove unused argument to CreateTargetScheduleState and change	Eric Christopher	2014-10-09	1	-2/+2
*	Add override to overriden virtual methods, remove virtual keywords.	Benjamin Kramer	2014-09-03	1	-1/+1
*	Canonicalize header guards into a common format.	Benjamin Kramer	2014-08-13	1	-3/+3
*	R600: Remove unused function	Matt Arsenault	2014-07-20	1	-1/+0
*	R600: Use LDS and vectors for private memory	Tom Stellard	2014-06-17	1	-0/+14
*	R600: Remove AMDIL instruction and register definitions	Tom Stellard	2014-06-13	1	-1/+0
*	R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtarget	Tom Stellard	2014-06-13	1	-2/+1
*	[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final...	Craig Topper	2014-04-29	1	-38/+38
*	[C++] Use 'nullptr'.	Craig Topper	2014-04-28	1	-1/+1
*	Fix known typos	Alp Toker	2014-01-24	1	-1/+1
*	R600: Implement TargetInstrInfo::isLegalToSplitMBBAt()	Tom Stellard	2013-11-22	1	-0/+2
*	R600: Fix scheduling of instructions that use the LDS output queue	Tom Stellard	2013-11-15	1	-0/+2
*	R600/SI: Add support for private address space load/store	Tom Stellard	2013-11-13	1	-8/+3
*	R600: Simplify handling of private address space	Tom Stellard	2013-10-22	1	-6/+7
*	R600: Remove unused InstrInfo::getMovImmInstr() function	Tom Stellard	2013-10-22	1	-3/+0
*	R600: add a pass that merges clauses.	Vincent Lejeune	2013-10-01	1	-0/+4
*	IfConverter: Use TargetSchedule for instruction latencies	Arnold Schwaighofer	2013-09-30	1	-0/+2
*	R600: Don't use trans slot for instructions that read LDS source registers	Tom Stellard	2013-09-12	1	-0/+1
*	R600: Add support for local memory atomic add	Tom Stellard	2013-09-05	1	-0/+6
*	R600: Use SchedModel enum for is{Trans,Vector}Only functions	Vincent Lejeune	2013-09-04	1	-0/+2
*	R600: Add IsExport bit to TableGen instruction definitions	Tom Stellard	2013-08-16	1	-0/+1
*	Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"	Tom Stellard	2013-07-31	1	-2/+0
*	R600: Use SchedModel enum for is{Trans,Vector}Only functions	Vincent Lejeune	2013-07-31	1	-0/+2
*	R600: Move CONST_ADDRESS folding into AMDGPUDAGToDAGISel::Select()	Tom Stellard	2013-07-23	1	-0/+7
*	R600: Support schedule and packetization of trans-only inst	Vincent Lejeune	2013-06-29	1	-10/+22
*	R600: Bank Swizzle now display SCL equivalent	Vincent Lejeune	2013-06-29	1	-5/+5
*	R600: Add local memory support via LDS	Tom Stellard	2013-06-28	1	-0/+11
*	R600: Add support for GROUP_BARRIER instruction	Tom Stellard	2013-06-28	1	-0/+2
*	R600: Use new getNamedOperandIdx function generated by TableGen	Tom Stellard	2013-06-25	1	-5/+3
*	R600: Rework subtarget info and remove AMDILDevice classes	Tom Stellard	2013-06-07	1	-1/+0
*	R600: Const/Neg/Abs can be folded to dot4	Vincent Lejeune	2013-06-04	1	-0/+2
*	R600: Relax some vector constraints on Dot4.	Vincent Lejeune	2013-05-17	1	-0/+5
*	R600: Some factorization	Vincent Lejeune	2013-05-17	1	-0/+28
*	R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips	Vincent Lejeune	2013-04-30	1	-0/+3
*	R600: Add FetchInst bit to instruction defs to denote vertex/tex instructions	Vincent Lejeune	2013-04-30	1	-0/+6
*	R600: Factorize maximum alu per clause in a single location	Vincent Lejeune	2013-04-03	1	-0/+1
*	R600: Factorize code handling Const Read Port limitation	Vincent Lejeune	2013-03-14	1	-0/+3
*	R600: Support for indirect addressing v4	Tom Stellard	2013-02-06	1	-0/+32
*	Resort the #include lines in include/... and lib/... with the	Chandler Carruth	2013-01-02	1	-2/+1
*	Add R600 backend	Tom Stellard	2012-12-11	1	-0/+169