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path: root/llvm/lib/Target/R600/R600InstrInfo.h
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* R600 -> AMDGPU renameTom Stellard2015-06-131-303/+0
| | | | llvm-svn: 239657
* [CodeGen] ArrayRef'ize cond/pred in various TII APIs. NFC.Ahmed Bougacha2015-06-111-4/+6
| | | | llvm-svn: 239553
* Remove unused argument to CreateTargetScheduleState and changeEric Christopher2014-10-091-2/+2
| | | | | | | the TargetMachine to a TargetSubtargetInfo since everything we wanted is off of that. llvm-svn: 219382
* Add override to overriden virtual methods, remove virtual keywords.Benjamin Kramer2014-09-031-1/+1
| | | | | | No functionality change. Changes made by clang-tidy + some manual cleanup. llvm-svn: 217028
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-3/+3
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* R600: Remove unused functionMatt Arsenault2014-07-201-1/+0
| | | | llvm-svn: 213472
* R600: Use LDS and vectors for private memoryTom Stellard2014-06-171-0/+14
| | | | llvm-svn: 211110
* R600: Remove AMDIL instruction and register definitionsTom Stellard2014-06-131-1/+0
| | | | | | Most of these are no longer used any more. llvm-svn: 210915
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-131-2/+1
| | | | llvm-svn: 210869
* [C++11] Add 'override' keywords and remove 'virtual'. Additionally add ↵Craig Topper2014-04-291-38/+38
| | | | | | 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. R600 edition llvm-svn: 207503
* [C++] Use 'nullptr'.Craig Topper2014-04-281-1/+1
| | | | llvm-svn: 207394
* Fix known typosAlp Toker2014-01-241-1/+1
| | | | | | | Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. llvm-svn: 200018
* R600: Implement TargetInstrInfo::isLegalToSplitMBBAt()Tom Stellard2013-11-221-0/+2
| | | | | | | | | | | | Splitting a basic block will create a new ALU clause, so we need to make sure we aren't moving uses of registers that are local to their current clause into a new one. I had a test case for this, but unfortunately unrelated schedule changes invalidated it, and I wasn't been able to come up with another one. NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195399
* R600: Fix scheduling of instructions that use the LDS output queueTom Stellard2013-11-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | The LDS output queue is accessed via the OQAP register. The OQAP register cannot be live across clauses, so if value is written to the output queue, it must be retrieved before the end of the clause. With the machine scheduler, we cannot statisfy this constraint, because it lacks proper alias analysis and it will mark some LDS accesses as having a chain dependency on vertex fetches. Since vertex fetches require a new clauses, the dependency may end up spiltting OQAP uses and defs so the end up in different clauses. See the lds-output-queue.ll test for a more detailed explanation. To work around this issue, we now combine the LDS read and the OQAP copy into one instruction and expand it after register allocation. This patch also adds some checks to the EmitClauseMarker pass, so that it doesn't end a clause with a value still in the output queue and removes AR.X and OQAP handling from the scheduler (AR.X uses and defs were already being expanded post-RA, so the scheduler will never see them). Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 194755
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-131-8/+3
| | | | | | | Private address space is emulated using the register file with MOVRELS and MOVRELD instructions. llvm-svn: 194626
* R600: Simplify handling of private address spaceTom Stellard2013-10-221-6/+7
| | | | | | | | | | | | | | | | | | The AMDGPUIndirectAddressing pass was previously responsible for lowering private loads and stores to indirect addressing instructions. However, this pass was buggy and way too complicated. The only advantage it had over the new simplified code was that it saved one instruction per direct write to private memory. This optimization likely has a minimal impact on performance, and we may be able to duplicate it using some other transformation. For the private address space, we now: 1. Lower private loads/store to Register(Load|Store) instructions 2. Reserve part of the register file as 'private memory' 3. After regalloc lower the Register(Load|Store) instructions to MOV instructions that use indirect addressing. llvm-svn: 193179
* R600: Remove unused InstrInfo::getMovImmInstr() functionTom Stellard2013-10-221-3/+0
| | | | llvm-svn: 193178
* R600: add a pass that merges clauses.Vincent Lejeune2013-10-011-0/+4
| | | | llvm-svn: 191790
* IfConverter: Use TargetSchedule for instruction latenciesArnold Schwaighofer2013-09-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For targets that have instruction itineraries this means no change. Targets that move over to the new schedule model will use be able the new schedule module for instruction latencies in the if-converter (the logic is such that if there is no itineary we will use the new sched model for the latencies). Before, we queried "TTI->getInstructionLatency()" for the instruction latency and the extra prediction cost. Now, we query the TargetSchedule abstraction for the instruction latency and TargetInstrInfo for the extra predictation cost. The TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if an itinerary exists, otherwise it will use the new schedule model. ATTENTION: Out of tree targets! (I will also send out an email later to LLVMDev) This means, if your target implements unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost); and returns a value for "PredCost", you now also need to implement unsigned getPredictationCost(const MachineInstr *MI); (if your target uses the IfConversion.cpp pass) radar://15077010 llvm-svn: 191671
* R600: Don't use trans slot for instructions that read LDS source registersTom Stellard2013-09-121-0/+1
| | | | | | | | | | | | | | | | This fixes some regressions in the piglit local memory store tests introduced by recent commits which made the scheduler aware of the trans slot. It's not possible to test this using lit, because there is no way to determine from the assembly dumps whether or not an instruction is in the trans slot. Even if this were possible, the test would be highly sensitive to changes in the scheduler and might generate confusing false negatives. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 190574
* R600: Add support for local memory atomic addTom Stellard2013-09-051-0/+6
| | | | llvm-svn: 190080
* R600: Use SchedModel enum for is{Trans,Vector}Only functionsVincent Lejeune2013-09-041-0/+2
| | | | llvm-svn: 189979
* R600: Add IsExport bit to TableGen instruction definitionsTom Stellard2013-08-161-0/+1
| | | | | Tested-by: Aaron Watry <awatry@gmail.com> llvm-svn: 188516
* Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"Tom Stellard2013-07-311-2/+0
| | | | | | This reverts commit 3f1de26cb5cc0543a6a1d71259a7a39d97139051. llvm-svn: 187524
* R600: Use SchedModel enum for is{Trans,Vector}Only functionsVincent Lejeune2013-07-311-0/+2
| | | | llvm-svn: 187512
* R600: Move CONST_ADDRESS folding into AMDGPUDAGToDAGISel::Select()Tom Stellard2013-07-231-0/+7
| | | | | | | | | | This increases the number of opportunites we have for folding. With the previous implementation we were unable to fold into any instructions other than the first when multiple instructions were selected from a single SDNode. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186919
* R600: Support schedule and packetization of trans-only instVincent Lejeune2013-06-291-10/+22
| | | | llvm-svn: 185268
* R600: Bank Swizzle now display SCL equivalentVincent Lejeune2013-06-291-5/+5
| | | | llvm-svn: 185267
* R600: Add local memory support via LDSTom Stellard2013-06-281-0/+11
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185162
* R600: Add support for GROUP_BARRIER instructionTom Stellard2013-06-281-0/+2
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185161
* R600: Use new getNamedOperandIdx function generated by TableGenTom Stellard2013-06-251-5/+3
| | | | llvm-svn: 184880
* R600: Rework subtarget info and remove AMDILDevice classesTom Stellard2013-06-071-1/+0
| | | | | | | | This should simplify the subtarget definitions and make it easier to add new ones. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183566
* R600: Const/Neg/Abs can be folded to dot4Vincent Lejeune2013-06-041-0/+2
| | | | llvm-svn: 183278
* R600: Relax some vector constraints on Dot4.Vincent Lejeune2013-05-171-0/+5
| | | | | | | | | | Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register coalescer to remove some unneeded COPY. This patch also defines some structures/functions that can be used to handle every vector instructions (CUBE, Cayman special instructions...) in a similar fashion. llvm-svn: 182126
* R600: Some factorizationVincent Lejeune2013-05-171-0/+28
| | | | llvm-svn: 182123
* R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chipsVincent Lejeune2013-04-301-0/+3
| | | | llvm-svn: 180759
* R600: Add FetchInst bit to instruction defs to denote vertex/tex instructionsVincent Lejeune2013-04-301-0/+6
| | | | | | v2[Vincent Lejeune]: Split FetchInst into usesTextureCache/usesVertexCache llvm-svn: 180755
* R600: Factorize maximum alu per clause in a single locationVincent Lejeune2013-04-031-0/+1
| | | | llvm-svn: 178667
* R600: Factorize code handling Const Read Port limitationVincent Lejeune2013-03-141-0/+3
| | | | llvm-svn: 177078
* R600: Support for indirect addressing v4Tom Stellard2013-02-061-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Only implemented for R600 so far. SI is missing implementations of a few callbacks used by the Indirect Addressing pass and needs code to handle frame indices. At the moment R600 only supports array sizes of 16 dwords or less. Register packing of vector types is currently disabled, which means that a vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order to correctly pack registers in all cases, we will need to implement an analysis pass for R600 that determines the correct vector width for each array. v2: - Add support for i8 zext load from stack. - Coding style fixes v3: - Don't reserve registers for indirect addressing when it isn't being used. - Fix bug caused by LLVM limiting the number of SubRegIndex declarations. v4: - Fix 64-bit defines llvm-svn: 174525
* Resort the #include lines in include/... and lib/... with theChandler Carruth2013-01-021-2/+1
| | | | | | | | | | utils/sort_includes.py script. Most of these are updating the new R600 target and fixing up a few regressions that have creeped in since the last time I sorted the includes. llvm-svn: 171362
* Add R600 backendTom Stellard2012-12-111-0/+169
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX llvm-svn: 169915
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