summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/R600/R600InstrInfo.cpp
Commit message (Expand)AuthorAgeFilesLines
* R600 -> AMDGPU renameTom Stellard2015-06-131-1435/+0
* [CodeGen] ArrayRef'ize cond/pred in various TII APIs. NFC.Ahmed Bougacha2015-06-111-7/+6
* Remove the need to cache the subtarget in the R600 TargetRegisterInfoEric Christopher2015-03-111-3/+1
* R600: Use c++11 style for loopJan Vesely2015-03-021-6/+4
* Remove unused argument to CreateTargetScheduleState and changeEric Christopher2014-10-091-5/+4
* Eliminate some deep std::vector copies. NFC.Benjamin Kramer2014-10-031-1/+1
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-1/+1
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-4/+4
* R600: Remove unused functionMatt Arsenault2014-07-201-5/+1
* R600: Make ShaderType privateMatt Arsenault2014-07-131-5/+9
* R600: Use LDS and vectors for private memoryTom Stellard2014-06-171-6/+63
* R600: Remove AMDIL instruction and register definitionsTom Stellard2014-06-131-10/+0
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-131-5/+3
* R600: Drop use of cached TargetMachine in R600InstrInfo.cppTom Stellard2014-06-131-1/+2
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-2/+2
* [cleanup] Lift using directives, DEBUG_TYPE definitions, and even someChandler Carruth2014-04-221-2/+2
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-3/+3
* R600: Remove successive JUMP in AnalyzeBranch when AllowModify is trueTom Stellard2014-01-231-1/+7
* R600: Implement TargetInstrInfo::isLegalToSplitMBBAt()Tom Stellard2013-11-221-0/+12
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-191-1/+1
* Revert r194865 and r194874.Alexey Samsonov2013-11-181-1/+1
* R600: Make dot_4 instructions predicableVincent Lejeune2013-11-161-0/+19
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-151-1/+1
* R600: Fix scheduling of instructions that use the LDS output queueTom Stellard2013-11-151-0/+8
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-131-47/+5
* R600: Simplify handling of private address spaceTom Stellard2013-10-221-11/+16
* R600: Remove unused InstrInfo::getMovImmInstr() functionTom Stellard2013-10-221-12/+0
* R600: add a pass that merges clauses.Vincent Lejeune2013-10-011-0/+18
* R600: Enable -verify-machineinstrs in some tests.Vincent Lejeune2013-10-011-0/+9
* IfConverter: Use TargetSchedule for instruction latenciesArnold Schwaighofer2013-09-301-0/+4
* R600: Don't use trans slot for instructions that read LDS source registersTom Stellard2013-09-121-0/+16
* R600: Use shared op optimization when checking cycle compatibilityVincent Lejeune2013-09-041-0/+2
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-09-041-0/+3
* R600: Use SchedModel enum for is{Trans,Vector}Only functionsVincent Lejeune2013-09-041-1/+11
* R600: Add support for i8 and i16 local memory storesTom Stellard2013-08-261-1/+2
* R600: Add IsExport bit to TableGen instruction definitionsTom Stellard2013-08-161-0/+4
* R600: Add 64-bit float load/store supportTom Stellard2013-08-011-8/+11
* Revert "R600: Non vector only instruction can be scheduled on trans unit"Tom Stellard2013-07-311-3/+0
* Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"Tom Stellard2013-07-311-11/+1
* R600: Avoid more than 4 literals in the same instruction group at schedulingVincent Lejeune2013-07-311-0/+5
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-07-311-0/+3
* R600: Use SchedModel enum for is{Trans,Vector}Only functionsVincent Lejeune2013-07-311-1/+11
* R600: Move CONST_ADDRESS folding into AMDGPUDAGToDAGISel::Select()Tom Stellard2013-07-231-0/+36
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector s...Craig Topper2013-07-141-1/+1
* Replacing an empty switch with its moral equivalent. No functional changes i...Aaron Ballman2013-07-101-3/+1
* R600: Do not predicated basic block with multiple alu clauseVincent Lejeune2013-07-091-0/+45
* R600: Fix an unitialized variable in R600InstrInfo.cppVincent Lejeune2013-06-301-1/+1
* R600: Unbreak GCC build.Benjamin Kramer2013-06-291-1/+2
* R600: Support schedule and packetization of trans-only instVincent Lejeune2013-06-291-39/+146
* R600: Bank Swizzle now display SCL equivalentVincent Lejeune2013-06-291-4/+4
OpenPOWER on IntegriCloud