summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/R600/R600InstrInfo.cpp
Commit message (Collapse)AuthorAgeFilesLines
* R600 -> AMDGPU renameTom Stellard2015-06-131-1435/+0
| | | | llvm-svn: 239657
* [CodeGen] ArrayRef'ize cond/pred in various TII APIs. NFC.Ahmed Bougacha2015-06-111-7/+6
| | | | llvm-svn: 239553
* Remove the need to cache the subtarget in the R600 TargetRegisterInfoEric Christopher2015-03-111-3/+1
| | | | | | classes. llvm-svn: 231954
* R600: Use c++11 style for loopJan Vesely2015-03-021-6/+4
| | | | | | Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <tom@stellard.net> llvm-svn: 230987
* Remove unused argument to CreateTargetScheduleState and changeEric Christopher2014-10-091-5/+4
| | | | | | | the TargetMachine to a TargetSubtargetInfo since everything we wanted is off of that. llvm-svn: 219382
* Eliminate some deep std::vector copies. NFC.Benjamin Kramer2014-10-031-1/+1
| | | | llvm-svn: 218999
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-1/+1
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-4/+4
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* R600: Remove unused functionMatt Arsenault2014-07-201-5/+1
| | | | llvm-svn: 213472
* R600: Make ShaderType privateMatt Arsenault2014-07-131-5/+9
| | | | llvm-svn: 212896
* R600: Use LDS and vectors for private memoryTom Stellard2014-06-171-6/+63
| | | | llvm-svn: 211110
* R600: Remove AMDIL instruction and register definitionsTom Stellard2014-06-131-10/+0
| | | | | | Most of these are no longer used any more. llvm-svn: 210915
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-131-5/+3
| | | | llvm-svn: 210869
* R600: Drop use of cached TargetMachine in R600InstrInfo.cppTom Stellard2014-06-131-1/+2
| | | | llvm-svn: 210868
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-2/+2
| | | | llvm-svn: 207197
* [cleanup] Lift using directives, DEBUG_TYPE definitions, and even someChandler Carruth2014-04-221-2/+2
| | | | | | | | | | | | system headers above the includes of generated '.inc' files that actually contain code. In a few targets this was already done pretty consistently, but it wasn't done *really* consistently anywhere. It is strictly cleaner IMO and necessary in a bunch of places where the DEBUG_TYPE is referenced from the generated code. Consistency with the necessary places trumps. Hopefully the build bots are OK with the movement of intrin.h... llvm-svn: 206838
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-3/+3
| | | | | | Remove the old functions. llvm-svn: 202636
* R600: Remove successive JUMP in AnalyzeBranch when AllowModify is trueTom Stellard2014-01-231-1/+7
| | | | | | | | | | | | This fixes a crash in the OpenCV OpenCL test suite. There is no lit test for this, because the test would be very large and could easily be invalidated by changes to the scheduler or other parts of the compiler. Patch by: Vincent Lejeune llvm-svn: 199919
* R600: Implement TargetInstrInfo::isLegalToSplitMBBAt()Tom Stellard2013-11-221-0/+12
| | | | | | | | | | | | Splitting a basic block will create a new ALU clause, so we need to make sure we aren't moving uses of registers that are local to their current clause into a new one. I had a test case for this, but unfortunately unrelated schedule changes invalidated it, and I wasn't been able to come up with another one. NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195399
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-191-1/+1
| | | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. The memory leaks in this version have been fixed. Thanks Alexey for pointing them out. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 195064
* Revert r194865 and r194874.Alexey Samsonov2013-11-181-1/+1
| | | | | | | | | | | | This change is incorrect. If you delete virtual destructor of both a base class and a subclass, then the following code: Base *foo = new Child(); delete foo; will not cause the destructor for members of Child class. As a result, I observe plently of memory leaks. Notable examples I investigated are: ObjectBuffer and ObjectBufferStream, AttributeImpl and StringSAttributeImpl. llvm-svn: 194997
* R600: Make dot_4 instructions predicableVincent Lejeune2013-11-161-0/+19
| | | | llvm-svn: 194927
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-151-1/+1
| | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 194865
* R600: Fix scheduling of instructions that use the LDS output queueTom Stellard2013-11-151-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | The LDS output queue is accessed via the OQAP register. The OQAP register cannot be live across clauses, so if value is written to the output queue, it must be retrieved before the end of the clause. With the machine scheduler, we cannot statisfy this constraint, because it lacks proper alias analysis and it will mark some LDS accesses as having a chain dependency on vertex fetches. Since vertex fetches require a new clauses, the dependency may end up spiltting OQAP uses and defs so the end up in different clauses. See the lds-output-queue.ll test for a more detailed explanation. To work around this issue, we now combine the LDS read and the OQAP copy into one instruction and expand it after register allocation. This patch also adds some checks to the EmitClauseMarker pass, so that it doesn't end a clause with a value still in the output queue and removes AR.X and OQAP handling from the scheduler (AR.X uses and defs were already being expanded post-RA, so the scheduler will never see them). Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 194755
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-131-47/+5
| | | | | | | Private address space is emulated using the register file with MOVRELS and MOVRELD instructions. llvm-svn: 194626
* R600: Simplify handling of private address spaceTom Stellard2013-10-221-11/+16
| | | | | | | | | | | | | | | | | | The AMDGPUIndirectAddressing pass was previously responsible for lowering private loads and stores to indirect addressing instructions. However, this pass was buggy and way too complicated. The only advantage it had over the new simplified code was that it saved one instruction per direct write to private memory. This optimization likely has a minimal impact on performance, and we may be able to duplicate it using some other transformation. For the private address space, we now: 1. Lower private loads/store to Register(Load|Store) instructions 2. Reserve part of the register file as 'private memory' 3. After regalloc lower the Register(Load|Store) instructions to MOV instructions that use indirect addressing. llvm-svn: 193179
* R600: Remove unused InstrInfo::getMovImmInstr() functionTom Stellard2013-10-221-12/+0
| | | | llvm-svn: 193178
* R600: add a pass that merges clauses.Vincent Lejeune2013-10-011-0/+18
| | | | llvm-svn: 191790
* R600: Enable -verify-machineinstrs in some tests.Vincent Lejeune2013-10-011-0/+9
| | | | llvm-svn: 191788
* IfConverter: Use TargetSchedule for instruction latenciesArnold Schwaighofer2013-09-301-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For targets that have instruction itineraries this means no change. Targets that move over to the new schedule model will use be able the new schedule module for instruction latencies in the if-converter (the logic is such that if there is no itineary we will use the new sched model for the latencies). Before, we queried "TTI->getInstructionLatency()" for the instruction latency and the extra prediction cost. Now, we query the TargetSchedule abstraction for the instruction latency and TargetInstrInfo for the extra predictation cost. The TargetSchedule abstraction will internally call "TTI->getInstructionLatency" if an itinerary exists, otherwise it will use the new schedule model. ATTENTION: Out of tree targets! (I will also send out an email later to LLVMDev) This means, if your target implements unsigned getInstrLatency(const InstrItineraryData *ItinData, const MachineInstr *MI, unsigned *PredCost); and returns a value for "PredCost", you now also need to implement unsigned getPredictationCost(const MachineInstr *MI); (if your target uses the IfConversion.cpp pass) radar://15077010 llvm-svn: 191671
* R600: Don't use trans slot for instructions that read LDS source registersTom Stellard2013-09-121-0/+16
| | | | | | | | | | | | | | | | This fixes some regressions in the piglit local memory store tests introduced by recent commits which made the scheduler aware of the trans slot. It's not possible to test this using lit, because there is no way to determine from the assembly dumps whether or not an instruction is in the trans slot. Even if this were possible, the test would be highly sensitive to changes in the scheduler and might generate confusing false negatives. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 190574
* R600: Use shared op optimization when checking cycle compatibilityVincent Lejeune2013-09-041-0/+2
| | | | llvm-svn: 189981
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-09-041-0/+3
| | | | llvm-svn: 189980
* R600: Use SchedModel enum for is{Trans,Vector}Only functionsVincent Lejeune2013-09-041-1/+11
| | | | llvm-svn: 189979
* R600: Add support for i8 and i16 local memory storesTom Stellard2013-08-261-1/+2
| | | | llvm-svn: 189223
* R600: Add IsExport bit to TableGen instruction definitionsTom Stellard2013-08-161-0/+4
| | | | | Tested-by: Aaron Watry <awatry@gmail.com> llvm-svn: 188516
* R600: Add 64-bit float load/store supportTom Stellard2013-08-011-8/+11
| | | | | | | | | | | | | | | | | * Added R600_Reg64 class * Added T#Index#.XY registers definition * Added v2i32 register reads from parameter and global space * Added f32 and i32 elements extraction from v2f32 and v2i32 * Added v2i32 -> v2f32 conversions Tom Stellard: - Mark vec2 operations as expand. The addition of a vec2 register class made them all legal. Patch by: Dmitry Cherkassov Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com> llvm-svn: 187582
* Revert "R600: Non vector only instruction can be scheduled on trans unit"Tom Stellard2013-07-311-3/+0
| | | | | | This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6. llvm-svn: 187526
* Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"Tom Stellard2013-07-311-11/+1
| | | | | | This reverts commit 3f1de26cb5cc0543a6a1d71259a7a39d97139051. llvm-svn: 187524
* R600: Avoid more than 4 literals in the same instruction group at schedulingVincent Lejeune2013-07-311-0/+5
| | | | llvm-svn: 187515
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-07-311-0/+3
| | | | llvm-svn: 187514
* R600: Use SchedModel enum for is{Trans,Vector}Only functionsVincent Lejeune2013-07-311-1/+11
| | | | llvm-svn: 187512
* R600: Move CONST_ADDRESS folding into AMDGPUDAGToDAGISel::Select()Tom Stellard2013-07-231-0/+36
| | | | | | | | | | This increases the number of opportunites we have for folding. With the previous implementation we were unable to fold into any instructions other than the first when multiple instructions were selected from a single SDNode. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 186919
* Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector ↵Craig Topper2013-07-141-1/+1
| | | | | | size. llvm-svn: 186274
* Replacing an empty switch with its moral equivalent. No functional changes ↵Aaron Ballman2013-07-101-3/+1
| | | | | | intended. llvm-svn: 186017
* R600: Do not predicated basic block with multiple alu clauseVincent Lejeune2013-07-091-0/+45
| | | | | | | | | Test is not included as it is several 1000 lines long. To test this functionnality, a test case must generate at least 2 ALU clauses, where an ALU clause is ~110 instructions long. NOTE: This is a candidate for the stable branch. llvm-svn: 185943
* R600: Fix an unitialized variable in R600InstrInfo.cppVincent Lejeune2013-06-301-1/+1
| | | | llvm-svn: 185294
* R600: Unbreak GCC build.Benjamin Kramer2013-06-291-1/+2
| | | | | | | operator++ on an enum is not legal. clang happens to accept it anyways, I think that's a known bug. llvm-svn: 185269
* R600: Support schedule and packetization of trans-only instVincent Lejeune2013-06-291-39/+146
| | | | llvm-svn: 185268
* R600: Bank Swizzle now display SCL equivalentVincent Lejeune2013-06-291-4/+4
| | | | llvm-svn: 185267
OpenPOWER on IntegriCloud