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path: root/llvm/lib/Target/R600/R600ISelLowering.cpp
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* Use makeArrayRef insted of calling ArrayRef<T> constructor directly. I introd...Craig Topper2014-04-301-1/+1
* R600: Remove duplicate setting of SELECT expansion.Tom Stellard2014-04-291-2/+0
* R600: Change UDIV/UREM to UDIVREM when legalizing typesTom Stellard2014-04-291-0/+5
* Convert SelectionDAG::getMergeValues to use ArrayRef.Craig Topper2014-04-271-5/+5
* Convert getMemIntrinsicNode to take ArrayRef of SDValue instead of pointer an...Craig Topper2014-04-261-1/+1
* Convert SelectionDAG::getNode methods to use ArrayRef<SDValue>.Craig Topper2014-04-261-15/+14
* R600: Minor cleanups.Matt Arsenault2014-04-181-13/+13
* R600: Expand sign extension of vectors.Matt Arsenault2014-04-161-0/+24
* Break PseudoSourceValue out of the Value hierarchy. It is now the root of its...Nick Lewycky2014-04-151-2/+2
* R600: Check if a sextload should be used for parameter loads.Matt Arsenault2014-04-111-1/+6
* R600: Match 24-bit arithmetic patterns in a Target DAGCombineTom Stellard2014-04-071-0/+1
* Use .data() instead of &x[0]Matt Arsenault2014-04-071-9/+11
* R600/SI: Fix unreachable with a sext_in_reg to an illegal type.Matt Arsenault2014-03-271-1/+3
* R600: Match sign_extend_inreg to BFE instructionsMatt Arsenault2014-03-171-0/+5
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-021-4/+4
* Fix known typosAlp Toker2014-01-241-3/+3
* R600/SI: Add support for i8 and i16 private loads/storesTom Stellard2014-01-221-0/+13
* Use llvm_unreachable instead of assert(0)Matt Arsenault2013-12-101-2/+2
* R600: Fix an infinite loop when trying to reorganize export/tex vector inputVincent Lejeune2013-12-101-5/+8
* Correct word hyphenationsAlp Toker2013-12-051-1/+1
* R600: Fix scheduling of instructions that use the LDS output queueTom Stellard2013-11-151-12/+8
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-131-15/+0
* R600: Fix selection failure on EXTLOADMatt Arsenault2013-11-131-1/+9
* R600: Reenable llvm.R600.load.input/interp.input for compatibilityVincent Lejeune2013-11-121-0/+45
* R600: Use function inputs to represent data stored in gprVincent Lejeune2013-11-111-37/+18
* Use isa<> instead of dyn_cast<> with unused valueMatt Arsenault2013-11-011-3/+3
* Fix a few typosMatt Arsenault2013-10-301-7/+7
* Prune utf8 chars in comments.NAKAMURA Takumi2013-10-281-2/+2
* Target/R600: Un-tab-ify.NAKAMURA Takumi2013-10-281-3/+3
* R600: Fix handling of vector kernel argumentsTom Stellard2013-10-231-8/+15
* R600: Use masked read sel for texture instructionsVincent Lejeune2013-10-131-0/+5
* R600: fix swizzle exportVincent Lejeune2013-10-131-5/+9
* R600: Add a ldptr intrinsic to support MSAA.Vincent Lejeune2013-10-021-1/+5
* R600: Fix handling of NAN in comparison instructionsTom Stellard2013-09-281-1/+8
* SelectionDAG: Improve legalization of SELECT_CC with illegal condition codesTom Stellard2013-09-281-4/+12
* SelectionDAG: Try to expand all condition codes using getCCSwappedOperands()Tom Stellard2013-09-281-28/+58
* R600: Move clamp handling code to R600IselLowering.cppVincent Lejeune2013-09-121-0/+16
* R600: Move code handling literal folding into R600ISelLowering.Vincent Lejeune2013-09-121-4/+59
* R600: Move fabs/fneg/sel folding logic into PostProcessIselVincent Lejeune2013-09-121-0/+179
* R600: Add support for local memory atomic addTom Stellard2013-09-051-7/+15
* R600: Expand SELECT nodes rather than custom lowering themTom Stellard2013-09-051-14/+6
* R600: Add support for vector local memory loadsTom Stellard2013-08-261-0/+8
* R600: Add support for i8 and i16 local memory loadsTom Stellard2013-08-261-14/+15
* R600: Add support for v4i32 and v2i32 local storesTom Stellard2013-08-261-1/+1
* R600: Expand vector float operations for both SI and R600Tom Stellard2013-08-161-9/+0
* R600: Add support for global vector stores with elements less than 32-bitsTom Stellard2013-08-161-1/+7
* R600: Add support for i16 and i8 global storesTom Stellard2013-08-161-12/+49
* R600: Set scheduling preference to Sched::SourceTom Stellard2013-08-121-1/+1
* R600: Add 64-bit float load/store supportTom Stellard2013-08-011-3/+18
* R600/SI: Expand vector fp <-> int conversionsTom Stellard2013-07-301-4/+0
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