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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-01-22 19:24:14 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-01-22 19:24:14 +0000 |
| commit | e93736057ff3ac73ed50b45c75665f78289bd5cc (patch) | |
| tree | 0a2c8f1cbeff1479449dce98ef503985fc6945cb /llvm/lib/Target/R600/R600ISelLowering.cpp | |
| parent | ec59e75ef28d237e3281fca614a333c6306e55b0 (diff) | |
| download | bcm5719-llvm-e93736057ff3ac73ed50b45c75665f78289bd5cc.tar.gz bcm5719-llvm-e93736057ff3ac73ed50b45c75665f78289bd5cc.zip | |
R600/SI: Add support for i8 and i16 private loads/stores
llvm-svn: 199823
Diffstat (limited to 'llvm/lib/Target/R600/R600ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/R600ISelLowering.cpp | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/R600ISelLowering.cpp b/llvm/lib/Target/R600/R600ISelLowering.cpp index 8d71919704d..03feabe23e6 100644 --- a/llvm/lib/Target/R600/R600ISelLowering.cpp +++ b/llvm/lib/Target/R600/R600ISelLowering.cpp @@ -1113,6 +1113,10 @@ SDValue R600TargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const { return SDValue(); } + SDValue Ret = AMDGPUTargetLowering::LowerSTORE(Op, DAG); + if (Ret.getNode()) { + return Ret; + } // Lowering for indirect addressing const MachineFunction &MF = DAG.getMachineFunction(); @@ -1204,6 +1208,15 @@ SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const SDValue Ptr = Op.getOperand(1); SDValue LoweredLoad; + SDValue Ret = AMDGPUTargetLowering::LowerLOAD(Op, DAG); + if (Ret.getNode()) { + SDValue Ops[2]; + Ops[0] = Ret; + Ops[1] = Chain; + return DAG.getMergeValues(Ops, 2, DL); + } + + if (LoadNode->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS && VT.isVector()) { SDValue MergedValues[2] = { SplitVectorLoad(Op, DAG), |
