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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-04-18 07:40:20 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-04-18 07:40:20 +0000 |
| commit | 209a7b92b5228b706b99322370381a76d32d8309 (patch) | |
| tree | 1c30e97a5e6cfacaee797b4b38411ed942d37556 /llvm/lib/Target/R600/R600ISelLowering.cpp | |
| parent | bc876017c2b9725f2b7792737baea7d086e63ac9 (diff) | |
| download | bcm5719-llvm-209a7b92b5228b706b99322370381a76d32d8309.tar.gz bcm5719-llvm-209a7b92b5228b706b99322370381a76d32d8309.zip | |
R600: Minor cleanups.
Fix indentation, better line wrapping, unused includes.
llvm-svn: 206562
Diffstat (limited to 'llvm/lib/Target/R600/R600ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/R600ISelLowering.cpp | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/llvm/lib/Target/R600/R600ISelLowering.cpp b/llvm/lib/Target/R600/R600ISelLowering.cpp index 37cac8960c9..ecffee23ded 100644 --- a/llvm/lib/Target/R600/R600ISelLowering.cpp +++ b/llvm/lib/Target/R600/R600ISelLowering.cpp @@ -1391,8 +1391,7 @@ SDValue R600TargetLowering::LowerFormalArguments( SmallVector<ISD::InputArg, 8> LocalIns; - getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins, - LocalIns); + getOriginalFunctionArgs(DAG, MF.getFunction(), Ins, LocalIns); AnalyzeFormalArguments(CCInfo, LocalIns); @@ -1427,28 +1426,29 @@ SDValue R600TargetLowering::LowerFormalArguments( DAG.getConstant(36 + VA.getLocMemOffset(), MVT::i32), MachinePointerInfo(UndefValue::get(PtrTy)), MemVT, false, false, 4); - // 4 is the preferred alignment for - // the CONSTANT memory space. + + // 4 is the preferred alignment for the CONSTANT memory space. InVals.push_back(Arg); } return Chain; } EVT R600TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { - if (!VT.isVector()) return MVT::i32; + if (!VT.isVector()) + return MVT::i32; return VT.changeVectorElementTypeToInteger(); } -static SDValue -CompactSwizzlableVector(SelectionDAG &DAG, SDValue VectorEntry, - DenseMap<unsigned, unsigned> &RemapSwizzle) { +static SDValue CompactSwizzlableVector( + SelectionDAG &DAG, SDValue VectorEntry, + DenseMap<unsigned, unsigned> &RemapSwizzle) { assert(VectorEntry.getOpcode() == ISD::BUILD_VECTOR); assert(RemapSwizzle.empty()); SDValue NewBldVec[4] = { - VectorEntry.getOperand(0), - VectorEntry.getOperand(1), - VectorEntry.getOperand(2), - VectorEntry.getOperand(3) + VectorEntry.getOperand(0), + VectorEntry.getOperand(1), + VectorEntry.getOperand(2), + VectorEntry.getOperand(3) }; for (unsigned i = 0; i < 4; i++) { @@ -1479,7 +1479,7 @@ CompactSwizzlableVector(SelectionDAG &DAG, SDValue VectorEntry, } return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(VectorEntry), - VectorEntry.getValueType(), NewBldVec, 4); + VectorEntry.getValueType(), NewBldVec, 4); } static SDValue ReorganizeVector(SelectionDAG &DAG, SDValue VectorEntry, |

