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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-09-28 02:50:50 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-09-28 02:50:50 +0000 |
| commit | 0351ea2010e01419aa35e9674587a14cfe559f90 (patch) | |
| tree | 65d667fcfb434153ce3bfd25e51ba422290e1ac6 /llvm/lib/Target/R600/R600ISelLowering.cpp | |
| parent | 5694d3090a9714de32a08ab56f62444996f65dff (diff) | |
| download | bcm5719-llvm-0351ea2010e01419aa35e9674587a14cfe559f90.tar.gz bcm5719-llvm-0351ea2010e01419aa35e9674587a14cfe559f90.zip | |
R600: Fix handling of NAN in comparison instructions
We were completely ignoring the unorder/ordered attributes of condition
codes and also incorrectly lowering seto and setuo.
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 191603
Diffstat (limited to 'llvm/lib/Target/R600/R600ISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/R600ISelLowering.cpp | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/llvm/lib/Target/R600/R600ISelLowering.cpp b/llvm/lib/Target/R600/R600ISelLowering.cpp index 5e9048a7019..e17dcd4b73f 100644 --- a/llvm/lib/Target/R600/R600ISelLowering.cpp +++ b/llvm/lib/Target/R600/R600ISelLowering.cpp @@ -38,10 +38,17 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) : computeRegisterProperties(); - setCondCodeAction(ISD::SETLE, MVT::f32, Expand); + // Set condition code actions + setCondCodeAction(ISD::SETO, MVT::f32, Expand); + setCondCodeAction(ISD::SETUO, MVT::f32, Expand); setCondCodeAction(ISD::SETLT, MVT::f32, Expand); + setCondCodeAction(ISD::SETLE, MVT::f32, Expand); setCondCodeAction(ISD::SETOLT, MVT::f32, Expand); setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); + setCondCodeAction(ISD::SETONE, MVT::f32, Expand); + setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); + setCondCodeAction(ISD::SETUGE, MVT::f32, Expand); + setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); setCondCodeAction(ISD::SETULT, MVT::f32, Expand); setCondCodeAction(ISD::SETULE, MVT::f32, Expand); |
