Commit message (Collapse) | Author | Age | Files | Lines | |
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* | PowerPCInstrInfo and PowerPCRegisterInfo have gone away; they are replaced | Misha Brukman | 2004-08-17 | 1 | -62/+0 |
| | | | | | | by 32- and 64-bit customized files, named appropriately. llvm-svn: 15856 | ||||
* | Set the is64bit flag and propagate it to PowerPCRegisterInfo | Misha Brukman | 2004-08-11 | 1 | -2/+4 |
| | | | | llvm-svn: 15671 | ||||
* | Renamed PPC32 (namespace for regs, opcodes) to PPC to include 64-bit targets | Misha Brukman | 2004-08-10 | 1 | -6/+6 |
| | | | | llvm-svn: 15631 | ||||
* | ADDI can take several forms, including: | Misha Brukman | 2004-07-26 | 1 | -2/+1 |
| | | | | | | | | | | addi r1, r2, 0 addi r1, <frame index #n>, 0 so we must check for the second parameter being a register for this instruction to be considered a reg-to-reg copy. llvm-svn: 15244 | ||||
* | assert() on MachineInstr properties instead of checking them dynamically | Misha Brukman | 2004-07-26 | 1 | -7/+8 |
| | | | | llvm-svn: 15243 | ||||
* | * Recognize `addi r1, r2, 0' a move instruction | Misha Brukman | 2004-07-26 | 1 | -2/+12 |
| | | | | | | * List formats of instructions currently recognized as moves llvm-svn: 15242 | ||||
* | Fix code formatting | Misha Brukman | 2004-07-16 | 1 | -21/+20 |
| | | | | llvm-svn: 14899 | ||||
* | Implement PowerPCInstrInfo::isMoveInstr(), patch by Nate Begeman | Misha Brukman | 2004-07-16 | 1 | -0/+29 |
| | | | | llvm-svn: 14898 | ||||
* | Initial revision | Misha Brukman | 2004-06-21 | 1 | -0/+22 |
llvm-svn: 14283 |