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authorMisha Brukman <brukman+llvm@gmail.com>2004-08-10 22:47:03 +0000
committerMisha Brukman <brukman+llvm@gmail.com>2004-08-10 22:47:03 +0000
commitdad438bfb98a10b3800c72e2da53a400c13cd407 (patch)
treecb0a052a66fd45f03faa76fdff49838c739a26b5 /llvm/lib/Target/PowerPC/PowerPCInstrInfo.cpp
parent0b9444e53614413d8744da4488b142f4363a035f (diff)
downloadbcm5719-llvm-dad438bfb98a10b3800c72e2da53a400c13cd407.tar.gz
bcm5719-llvm-dad438bfb98a10b3800c72e2da53a400c13cd407.zip
Renamed PPC32 (namespace for regs, opcodes) to PPC to include 64-bit targets
llvm-svn: 15631
Diffstat (limited to 'llvm/lib/Target/PowerPC/PowerPCInstrInfo.cpp')
-rw-r--r--llvm/lib/Target/PowerPC/PowerPCInstrInfo.cpp12
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/PowerPC/PowerPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PowerPCInstrInfo.cpp
index ba14b36baf1..17b0989e1f4 100644
--- a/llvm/lib/Target/PowerPC/PowerPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PowerPCInstrInfo.cpp
@@ -26,32 +26,32 @@ bool PowerPCInstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const {
MachineOpCode oc = MI.getOpcode();
- if (oc == PPC32::OR) { // or r1, r2, r2
+ if (oc == PPC::OR) { // or r1, r2, r2
assert(MI.getNumOperands() == 3 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
MI.getOperand(2).isRegister() &&
- "invalid PPC32 OR instruction!");
+ "invalid PPC OR instruction!");
if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
}
- } else if (oc == PPC32::ADDI) { // addi r1, r2, 0
+ } else if (oc == PPC::ADDI) { // addi r1, r2, 0
assert(MI.getNumOperands() == 3 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(2).isImmediate() &&
- "invalid PPC32 ADDI instruction!");
+ "invalid PPC ADDI instruction!");
if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
}
- } else if (oc == PPC32::FMR) { // fmr r1, r2
+ } else if (oc == PPC::FMR) { // fmr r1, r2
assert(MI.getNumOperands() == 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
- "invalid PPC32 FMR instruction");
+ "invalid PPC FMR instruction");
sourceReg = MI.getOperand(1).getReg();
destReg = MI.getOperand(0).getReg();
return true;
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