summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/PowerPC/PowerPCInstrInfo.cpp
diff options
context:
space:
mode:
authorMisha Brukman <brukman+llvm@gmail.com>2004-07-26 21:29:00 +0000
committerMisha Brukman <brukman+llvm@gmail.com>2004-07-26 21:29:00 +0000
commit43f1c4045a5a7c141fe9eb429ad9e042b6f006aa (patch)
treeb0f08feb8d8671395666944fec1fcc15950a15b5 /llvm/lib/Target/PowerPC/PowerPCInstrInfo.cpp
parent7f50013b0e8aa9d0b4cdf894b30d928c92b5647e (diff)
downloadbcm5719-llvm-43f1c4045a5a7c141fe9eb429ad9e042b6f006aa.tar.gz
bcm5719-llvm-43f1c4045a5a7c141fe9eb429ad9e042b6f006aa.zip
* Recognize `addi r1, r2, 0' a move instruction
* List formats of instructions currently recognized as moves llvm-svn: 15242
Diffstat (limited to 'llvm/lib/Target/PowerPC/PowerPCInstrInfo.cpp')
-rw-r--r--llvm/lib/Target/PowerPC/PowerPCInstrInfo.cpp14
1 files changed, 12 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PowerPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PowerPCInstrInfo.cpp
index 490ed18c5c7..40fb18ba477 100644
--- a/llvm/lib/Target/PowerPC/PowerPCInstrInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PowerPCInstrInfo.cpp
@@ -26,7 +26,7 @@ bool PowerPCInstrInfo::isMoveInstr(const MachineInstr& MI,
unsigned& sourceReg,
unsigned& destReg) const {
MachineOpCode oc = MI.getOpcode();
- if (oc == PPC32::OR) {
+ if (oc == PPC32::OR) { // or r1, r2, r2
assert(MI.getNumOperands() == 3 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
@@ -37,7 +37,17 @@ bool PowerPCInstrInfo::isMoveInstr(const MachineInstr& MI,
destReg = MI.getOperand(0).getReg();
return true;
}
- } else if (oc == PPC32::FMR) {
+ } else if (oc == PPC32::ADDI) { // addi r1, r2, 0
+ if (MI.getNumOperands() == 3 &&
+ MI.getOperand(0).isRegister() &&
+ MI.getOperand(1).isRegister() &&
+ MI.getOperand(2).isImmediate() &&
+ MI.getOperand(2).getImmedValue() == 0) {
+ sourceReg = MI.getOperand(1).getReg();
+ destReg = MI.getOperand(0).getReg();
+ return true;
+ }
+ } else if (oc == PPC32::FMR) { // fmr r1, r2
assert(MI.getNumOperands() == 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
OpenPOWER on IntegriCloud