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path: root/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
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* Revert "[llvm] r359313 - [PowerPC] Update P9 vector costs for insert/extract ...David L. Jones2019-05-011-29/+0
* Fix operator precedence warning. NFCI.Simon Pilgrim2019-04-291-1/+2
* [PowerPC] Update P9 vector costs for insert/extract elementRoland Froese2019-04-261-0/+29
* test commit (add blank line) NFCRoland Froese2019-02-011-0/+1
* [PowerPC] Update Vector Costs for P9Nemanja Ivanovic2019-01-261-11/+46
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [LV] Support vectorization of interleave-groups that require an epilog underDorit Nuzman2018-10-311-3/+5
* recommit 344472 after fixing build failure on ARM and PPC.Dorit Nuzman2018-10-141-1/+6
* revert 344472 due to failures.Dorit Nuzman2018-10-141-6/+1
* [IAI,LV] Add support for vectorizing predicated strided accesses using maskedDorit Nuzman2018-10-141-1/+6
* Remove trailing spaceFangrui Song2018-07-301-1/+1
* Revert "[PowerPC] LSR tunings for PowerPC"Stefan Pintilie2018-03-091-13/+0
* [PowerPC] LSR tunings for PowerPCStefan Pintilie2018-03-071-0/+13
* Re-commit : [PowerPC] Add handling for ColdCC calling convention and a pass t...Zaara Syeda2018-01-301-0/+13
* Revert [PowerPC] This reverts commit rL322721Zaara Syeda2018-01-171-13/+0
* [PowerPC] Add handling for ColdCC calling convention and a pass to markZaara Syeda2018-01-171-0/+13
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-2/+2
* [CodeGen][ExpandMemcmp] Allow memcmp to expand to vector loads (2).Clement Courbet2017-10-301-3/+11
* The cost of splitting a large vector instruction is not being taken into acco...Graham Yiu2017-10-191-0/+11
* [CodeGenPrepare][NFC] Rename TargetTransformInfo::expandMemCmp -> TargetTrans...Clement Courbet2017-09-251-1/+1
* [LoopUnroll] Pass SCEV to getUnrollingPreferences hook. NFCI.Geoff Berry2017-06-281-2/+2
* Const correctness for TTI::getRegisterBitWidthDaniel Neilson2017-06-121-1/+1
* [PowerPC] Correctly specify the cache line size for Power 7, 8 and 9.Sean Fertile2017-05-311-3/+12
* [PPC] Inline expansion of memcmpZaara Syeda2017-05-311-0/+5
* [SystemZ] TargetTransformInfo cost functions implemented.Jonas Paulsson2017-04-121-4/+6
* [PPC] Give unaligned memory access lower cost on processor that supports itGuozhi Wei2017-02-171-0/+4
* Revert "[PPC] Give unaligned memory access lower cost on processor that suppo...Daniel Jasper2017-01-251-4/+0
* [PPC] Give unaligned memory access lower cost on processor that supports itGuozhi Wei2017-01-201-0/+4
* [X86] updating TTI costs for arithmetic instructions on X86\SLM arch.Mohammed Agabaria2017-01-111-1/+1
* [ppc] Correctly compute the cost of loading 32/64 bit memory into VSRGuozhi Wei2016-12-031-5/+14
* Replace "fallthrough" comments with LLVM_FALLTHROUGHJustin Bogner2016-08-171-3/+4
* [Power9] Add support for -mcpu=pwr9 in the back endNemanja Ivanovic2016-05-091-2/+3
* [PPC] Remove -ppc-loop-prefetch-distance in favor of -prefetch-distanceAdam Nemet2016-03-291-7/+5
* [PowerPC] Refactor popcnt[dw] target featuresHal Finkel2016-03-291-2/+3
* [PowerPC] Clarify a comment in PPCTTI about vector loadsHal Finkel2016-03-281-1/+1
* [PowerPC] On the A2, popcnt[dw] are very slowHal Finkel2016-03-281-1/+1
* [TTI] Add getPrefetchDistance from PPCLoopDataPrefetch, NFCAdam Nemet2016-01-271-0/+8
* [TTI] Add getCacheLineSizeAdam Nemet2016-01-211-0/+12
* [PowerPC] Enable interleaved-access vectorizationHal Finkel2015-09-041-1/+37
* [PowerPC] Always use aggressive interleaving on the A2Hal Finkel2015-09-031-0/+7
* [PowerPC] Include the permutation cost for unaligned vector loadsHal Finkel2015-09-031-8/+12
* [PowerPC] Cleanup cost model for unaligned vector loads/storesHal Finkel2015-09-021-22/+37
* [TTI] Make the cost APIs in TargetTransformInfo consistently use 'int'Chandler Carruth2015-08-051-18/+15
* Make TargetLowering::getPointerTy() taking DataLayout as an argumentMehdi Amini2015-07-091-1/+1
* [PPC/LoopUnrollRuntime] Don't avoid high-cost trip count computation on the P...Hal Finkel2015-05-211-0/+4
* [X86] Disable loop unrolling in loop vectorization pass when VF is 1.Wei Mi2015-05-061-1/+1
* Do not restrict interleaved unrolling to small loops, depending on the target.Olivier Sallenave2015-03-061-0/+4
* [PowerPC] Add support for the QPX vector instruction setHal Finkel2015-02-251-1/+8
* Change max interleave factor to 12 for POWER7 and POWER8.Olivier Sallenave2015-02-121-0/+6
* [multiversion] Remove the function parameter from the unrollingChandler Carruth2015-02-011-2/+2
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