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path: root/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp
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* [PowerPC][LoopVectorize] Extend getRegisterClassForType to consider double an...Jinsong Ji2020-01-061-3/+9
* Delete llvm.{sig,}{setjmp,longjmp} remnant after r136821Fangrui Song2019-12-271-18/+0
* [PowerPC] Add missing legalization for vector BSWAPNemanja Ivanovic2019-12-171-0/+14
* Rename TTI::getIntImmCost for instructions and intrinsicsReid Kleckner2019-12-111-6/+6
* [ARM] Teach the Arm cost model that a Shift can be folded into other instruct...David Green2019-12-091-4/+7
* [PowerPC] Add new Future CPU for PowerPC in LLVMStefan Pintilie2019-11-271-2/+4
* [PowerPC] Rename DarwinDirective to CPUDirective (NFC)Kit Barton2019-11-251-4/+4
* [PowerPC] Do not emit HW loop if the body contains calls to lrint/lroundNemanja Ivanovic2019-10-281-0/+4
* [Alignment][NFC] getMemoryOpCost uses MaybeAlignGuillaume Chatelet2019-10-251-4/+7
* recommit: [LoopVectorize][PowerPC] Estimate int and float register pressure s...Zi Xuan Wu2019-10-121-4/+31
* [System Model] [TTI] Update cache and prefetch TTI interfacesDavid Greene2019-10-091-2/+2
* Revert "[LoopVectorize][PowerPC] Estimate int and float register pressure sep...Jinsong Ji2019-10-081-31/+4
* [LoopVectorize][PowerPC] Estimate int and float register pressure separately ...Zi Xuan Wu2019-10-081-4/+31
* Recommit [PowerPC] Update P9 vector costs for insert/extractRoland Froese2019-08-261-0/+29
* Revert "[System Model] [TTI] Update cache and prefetch TTI interfaces"David Greene2019-07-101-2/+2
* [System Model] [TTI] Update cache and prefetch TTI interfacesDavid Greene2019-07-101-2/+2
* [PowerPC] exclude ICmpZero in LSR if icmp can be replaced in later hardware l...Chen Zheng2019-07-031-0/+22
* Revert Recommit [PowerPC] Update P9 vector costs for insert/extract elementJordan Rupprecht2019-07-011-29/+0
* Recommit [PowerPC] Update P9 vector costs for insert/extract elementRoland Froese2019-06-271-0/+29
* [ExpandMemCmp] Move all options to TargetTransformInfo.Clement Courbet2019-06-251-11/+6
* [NFC] move some hardware loop checking code to a common place for other using.Chen Zheng2019-06-191-1/+1
* [CodeGen] Generic Hardware Loop SupportSam Parker2019-06-071-0/+344
* Revert "[llvm] r359313 - [PowerPC] Update P9 vector costs for insert/extract ...David L. Jones2019-05-011-29/+0
* Fix operator precedence warning. NFCI.Simon Pilgrim2019-04-291-1/+2
* [PowerPC] Update P9 vector costs for insert/extract elementRoland Froese2019-04-261-0/+29
* test commit (add blank line) NFCRoland Froese2019-02-011-0/+1
* [PowerPC] Update Vector Costs for P9Nemanja Ivanovic2019-01-261-11/+46
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [LV] Support vectorization of interleave-groups that require an epilog underDorit Nuzman2018-10-311-3/+5
* recommit 344472 after fixing build failure on ARM and PPC.Dorit Nuzman2018-10-141-1/+6
* revert 344472 due to failures.Dorit Nuzman2018-10-141-6/+1
* [IAI,LV] Add support for vectorizing predicated strided accesses using maskedDorit Nuzman2018-10-141-1/+6
* Remove trailing spaceFangrui Song2018-07-301-1/+1
* Revert "[PowerPC] LSR tunings for PowerPC"Stefan Pintilie2018-03-091-13/+0
* [PowerPC] LSR tunings for PowerPCStefan Pintilie2018-03-071-0/+13
* Re-commit : [PowerPC] Add handling for ColdCC calling convention and a pass t...Zaara Syeda2018-01-301-0/+13
* Revert [PowerPC] This reverts commit rL322721Zaara Syeda2018-01-171-13/+0
* [PowerPC] Add handling for ColdCC calling convention and a pass to markZaara Syeda2018-01-171-0/+13
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-2/+2
* [CodeGen][ExpandMemcmp] Allow memcmp to expand to vector loads (2).Clement Courbet2017-10-301-3/+11
* The cost of splitting a large vector instruction is not being taken into acco...Graham Yiu2017-10-191-0/+11
* [CodeGenPrepare][NFC] Rename TargetTransformInfo::expandMemCmp -> TargetTrans...Clement Courbet2017-09-251-1/+1
* [LoopUnroll] Pass SCEV to getUnrollingPreferences hook. NFCI.Geoff Berry2017-06-281-2/+2
* Const correctness for TTI::getRegisterBitWidthDaniel Neilson2017-06-121-1/+1
* [PowerPC] Correctly specify the cache line size for Power 7, 8 and 9.Sean Fertile2017-05-311-3/+12
* [PPC] Inline expansion of memcmpZaara Syeda2017-05-311-0/+5
* [SystemZ] TargetTransformInfo cost functions implemented.Jonas Paulsson2017-04-121-4/+6
* [PPC] Give unaligned memory access lower cost on processor that supports itGuozhi Wei2017-02-171-0/+4
* Revert "[PPC] Give unaligned memory access lower cost on processor that suppo...Daniel Jasper2017-01-251-4/+0
* [PPC] Give unaligned memory access lower cost on processor that supports itGuozhi Wei2017-01-201-0/+4
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