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| author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2016-05-09 18:54:58 +0000 |
|---|---|---|
| committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2016-05-09 18:54:58 +0000 |
| commit | 6e29baf7f529fe7e5fbd1bff1037a02ef7e25a28 (patch) | |
| tree | 99cd6680860575e5a08e1d5dc04646caf2b4fa9e /llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp | |
| parent | da7fe0c4a4954145844c01d86886a7b77b70f861 (diff) | |
| download | bcm5719-llvm-6e29baf7f529fe7e5fbd1bff1037a02ef7e25a28.tar.gz bcm5719-llvm-6e29baf7f529fe7e5fbd1bff1037a02ef7e25a28.zip | |
[Power9] Add support for -mcpu=pwr9 in the back end
This patch corresponds to review:
http://reviews.llvm.org/D19683
Simply adds the bits for being able to specify -mcpu=pwr9 to the back end.
llvm-svn: 268950
Diffstat (limited to 'llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp index 85a684a8929..9331e41fb9c 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp @@ -267,8 +267,9 @@ unsigned PPCTTIImpl::getMaxInterleaveFactor(unsigned VF) { // For P7 and P8, floating-point instructions have a 6-cycle latency and // there are two execution units, so unroll by 12x for latency hiding. - if (Directive == PPC::DIR_PWR7 || - Directive == PPC::DIR_PWR8) + // FIXME: the same for P9 as previous gen until POWER9 scheduling is ready + if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 || + Directive == PPC::DIR_PWR9) return 12; // For most things, modern systems have two execution units (and |
