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path: root/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
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* [mips] Fix a small typo that would leave BLTZC out of getAnalyzableBrOpc().'Vasileios Kalintiris2016-04-221-1/+1
* [NFC] Header cleanupMehdi Amini2016-04-181-2/+1
* [mips] MIPS32R6 compact branch supportDaniel Sanders2016-03-141-2/+14
* [mips] Remove redundant inclusions of MipsAnalyzeImmediate.hDaniel Sanders2016-02-031-0/+1
* [mips] Correct operand order in DSP's mthi/mtloDaniel Sanders2016-01-121-2/+3
* [mips] Interrupt attribute support for mips32r2+.Vasileios Kalintiris2015-10-261-2/+76
* [mips] Remove incorrect DebugLoc entries from prologuePetar Jovanovic2015-08-281-2/+1
* [mips] Remap move as or.Vasileios Kalintiris2015-08-111-2/+2
* [mips] Move ABI-dependent register selections to MipsABIInfo. NFC.Daniel Sanders2015-04-171-4/+5
* [mips] Make sure that we don't adjust the stack pointer by zero amount.Vasileios Kalintiris2015-04-021-0/+3
* Remove the need to cache the subtarget in the Mips TargetRegisterInfoEric Christopher2015-03-121-1/+1
* Fix a couple of odd formatting issues.Eric Christopher2015-01-081-6/+4
* This routine is in InstrInfo, there's no need to access it again.Eric Christopher2015-01-081-8/+3
* Remove dead variable.Eric Christopher2015-01-061-1/+1
* [mips][microMIPS] This patch implements functionality in MIPS delay slotJozef Kolek2014-11-211-1/+3
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-3/+6
* Make InstrInfo depend only upon the Subtarget getting passed inEric Christopher2014-07-181-24/+22
* [mips] For the FP64A ABI, odd-numbered double-precision moves must not use mt...Daniel Sanders2014-07-141-3/+21
* [mips] Use MFHC1 when it is available (MIPS32r2 and later) for both FP32 and ...Daniel Sanders2014-07-141-4/+5
* [mips] Expand BuildPairF64 to a spill and reload when the O32 FPXX ABI isSasa Stankovic2014-07-141-10/+9
* [mips][mips64r6] Use JALR for returns instead of JR (which is not available o...Daniel Sanders2014-07-091-11/+15
* [mips] Use MTHC1 when it is available (MIPS32r2 and later) for both FP32 and ...Daniel Sanders2014-06-121-10/+21
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-1/+1
* Implementation of 16-bit microMIPS instructions MFHI and MFLO.Zoran Jovanovic2014-04-031-7/+13
* Implementation of microMIPS 16-bit instructions MOVE and JALR.Zoran Jovanovic2014-03-201-3/+7
* [mips][fp64] Add an implicit def to MTHC1 claiming that it reads the lower 32...Daniel Sanders2014-03-121-8/+20
* [mips][fp64] Add an implicit def to MFHC1 claiming that it reads the lower 32...Daniel Sanders2014-03-101-3/+15
* [C++11] Replace llvm::tie with std::tie.Benjamin Kramer2014-03-021-1/+2
* [mips] Fix 'ran out of registers' in MIPS32 with FP64 when generating code fo...Daniel Sanders2013-11-181-2/+7
* [mips] Define a pseudo instruction which writes to both the lower and higherAkira Hatanaka2013-10-151-0/+38
* [mips] Fix definition of mfhi and mflo instructions to read from the wholeAkira Hatanaka2013-10-071-0/+18
* [mips][msa] Added support for MSA registers to copyPhysRegDaniel Sanders2013-09-271-0/+4
* [mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index doubleAkira Hatanaka2013-09-071-61/+0
* [mips][msa] Added cfcmsa, and ctcmsaDaniel Sanders2013-08-281-0/+4
* [mips][msa] Added spill/reload supportDaniel Sanders2013-08-271-0/+16
* [mips] Add support for mfhc1 and mthc1.Akira Hatanaka2013-08-201-8/+23
* [mips] Define register class FGRH32 for the high half of the 64-bit floatingAkira Hatanaka2013-08-201-8/+7
* [mips] Resolve register classes dynamically using ptr_rc to reduce the number ofAkira Hatanaka2013-08-201-24/+20
* [mips] Rename HIRegs and LORegs.Akira Hatanaka2013-08-141-12/+12
* [mips] Rename accumulator register classes and FP register operands.Akira Hatanaka2013-08-081-12/+12
* [mips] Rename register classes CPURegs and CPU64Regs.Akira Hatanaka2013-08-061-11/+11
* [mips] Use ADDu instead of OR to copy general purpose registers. Also, deleteAkira Hatanaka2013-07-221-6/+5
* [mips] Delete MFC1_FT_CCR, MTC1_FT_CCR and MOVCCRToCCR.Akira Hatanaka2013-07-191-2/+0
* [mips] Use function TargetInstrInfo::getRegClass.Akira Hatanaka2013-06-111-5/+7
* [mips] Use a helper function which compares the size of the source andAkira Hatanaka2013-06-081-6/+18
* Don't cache the instruction and register info from the TargetMachine, becauseBill Wendling2013-06-071-1/+1
* [mips] Fix instruction selection pattern for sint_to_fp node to avoid emittin...Akira Hatanaka2013-05-161-0/+37
* [mips] Add option -mno-ldc1-sdc1.Akira Hatanaka2013-05-131-0/+62
* [mips] Rename functions. No functionality changes.Akira Hatanaka2013-05-131-11/+11
* [mips] Handle reading, writing or copying of ccond field of DSP controlAkira Hatanaka2013-05-021-0/+15
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