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authorDaniel Sanders <daniel.sanders@imgtec.com>2013-08-28 10:26:24 +0000
committerDaniel Sanders <daniel.sanders@imgtec.com>2013-08-28 10:26:24 +0000
commitf9aa1d1902e060986ef1edcd2d9830f6f6f85c08 (patch)
treeaf9258ac113242e6f1ef41ddef271768c090d403 /llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
parent0dc0dd464b6f68340b71f1213aa32ddabed7e067 (diff)
downloadbcm5719-llvm-f9aa1d1902e060986ef1edcd2d9830f6f6f85c08.tar.gz
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[mips][msa] Added cfcmsa, and ctcmsa
The MSA control registers have been added as reserved registers, and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered into these nodes. llvm-svn: 189468
Diffstat (limited to 'llvm/lib/Target/Mips/MipsSEInstrInfo.cpp')
-rw-r--r--llvm/lib/Target/Mips/MipsSEInstrInfo.cpp4
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
index e7967a8dea7..374837e37d2 100644
--- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
@@ -110,6 +110,8 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
.addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
return;
}
+ else if (Mips::MSACtrlRegClass.contains(SrcReg))
+ Opc = Mips::CFCMSA;
}
else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
if (Mips::CCRRegClass.contains(DestReg))
@@ -130,6 +132,8 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
.addReg(DestReg, RegState::ImplicitDefine);
return;
}
+ else if (Mips::MSACtrlRegClass.contains(DestReg))
+ Opc = Mips::CTCMSA;
}
else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
Opc = Mips::FMOV_S;
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