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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-08-27 10:04:21 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2013-08-27 10:04:21 +0000 |
| commit | b8bce4d935959744842bff61ab32384669b64e9e (patch) | |
| tree | d34fd455d924a01f11e68194f9bfd3c54ddf41bf /llvm/lib/Target/Mips/MipsSEInstrInfo.cpp | |
| parent | 5e318f0bfeb6276a1db0656a9719d1de520f1ed5 (diff) | |
| download | bcm5719-llvm-b8bce4d935959744842bff61ab32384669b64e9e.tar.gz bcm5719-llvm-b8bce4d935959744842bff61ab32384669b64e9e.zip | |
[mips][msa] Added spill/reload support
llvm-svn: 189332
Diffstat (limited to 'llvm/lib/Target/Mips/MipsSEInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsSEInstrInfo.cpp | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp index a81db7fab75..e7967a8dea7 100644 --- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -199,6 +199,14 @@ storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Opc = Mips::SDC1; else if (Mips::FGR64RegClass.hasSubClassEq(RC)) Opc = Mips::SDC164; + else if (RC->hasType(MVT::v16i8)) + Opc = Mips::ST_B; + else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16)) + Opc = Mips::ST_H; + else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32)) + Opc = Mips::ST_W; + else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64)) + Opc = Mips::ST_D; assert(Opc && "Register class not handled!"); BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) @@ -232,6 +240,14 @@ loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, Opc = Mips::LDC1; else if (Mips::FGR64RegClass.hasSubClassEq(RC)) Opc = Mips::LDC164; + else if (RC->hasType(MVT::v16i8)) + Opc = Mips::LD_B; + else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16)) + Opc = Mips::LD_H; + else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32)) + Opc = Mips::LD_W; + else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64)) + Opc = Mips::LD_D; assert(Opc && "Register class not handled!"); BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset) |
