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| author | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2014-03-20 10:18:24 +0000 |
|---|---|---|
| committer | Zoran Jovanovic <zoran.jovanovic@imgtec.com> | 2014-03-20 10:18:24 +0000 |
| commit | 87d13e5ec16abf645f1b0418c001340db397c34a (patch) | |
| tree | b7268e703d019f4f997a58e23e4613666a53b1b7 /llvm/lib/Target/Mips/MipsSEInstrInfo.cpp | |
| parent | 9cf08c46a6088a1025f38a2629a13d434684f320 (diff) | |
| download | bcm5719-llvm-87d13e5ec16abf645f1b0418c001340db397c34a.tar.gz bcm5719-llvm-87d13e5ec16abf645f1b0418c001340db397c34a.zip | |
Implementation of microMIPS 16-bit instructions MOVE and JALR.
Differential Revision: http://llvm-reviews.chandlerc.com/D3112
llvm-svn: 204325
Diffstat (limited to 'llvm/lib/Target/Mips/MipsSEInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsSEInstrInfo.cpp | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp index 195ad8ee1cc..3393dafe1d3 100644 --- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -84,11 +84,15 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, unsigned DestReg, unsigned SrcReg, bool KillSrc) const { unsigned Opc = 0, ZeroReg = 0; + bool isMicroMips = TM.getSubtarget<MipsSubtarget>().inMicroMipsMode(); if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. - if (Mips::GPR32RegClass.contains(SrcReg)) - Opc = Mips::ADDu, ZeroReg = Mips::ZERO; - else if (Mips::CCRRegClass.contains(SrcReg)) + if (Mips::GPR32RegClass.contains(SrcReg)) { + if (isMicroMips) + Opc = Mips::MOVE16_MM; + else + Opc = Mips::ADDu, ZeroReg = Mips::ZERO; + } else if (Mips::CCRRegClass.contains(SrcReg)) Opc = Mips::CFC1; else if (Mips::FGR32RegClass.contains(SrcReg)) Opc = Mips::MFC1; |
