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path: root/llvm/lib/Target/Mips/MipsISelLowering.cpp
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* Fix a bug in MipsTargetLowering::LowerLOAD. A shift-right-logical node isAkira Hatanaka2012-06-041-1/+2
| | | | | | inserted after the shift-left-logical node. llvm-svn: 157937
* MIPS TLS: use the model selected by TargetMachine::getTLSModel().Hans Wennborg2012-06-041-3/+4
| | | | | | This was mostly done already in r156162, but I missed one place. llvm-svn: 157929
* remove an unused variable.Chris Lattner2012-06-021-1/+1
| | | | llvm-svn: 157872
* Set operation actions for load/store nodes in the Mips backend.Akira Hatanaka2012-06-021-0/+11
| | | | llvm-svn: 157866
* Define functions MipsTargetLowering::LowerLOAD and LowerSTORE whichAkira Hatanaka2012-06-021-0/+138
| | | | | | custom-lower unaligned load and store nodes. llvm-svn: 157864
* Define Mips specific unaligned load/store nodes.Akira Hatanaka2012-06-021-0/+8
| | | | llvm-svn: 157863
* Expand unaligned i16 loads/stores for the Mips backend.Akira Hatanaka2012-06-021-1/+0
| | | | | | | | This is the first of a series of patches which make changes to the backend to emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction selection. llvm-svn: 157862
* Cleanup and factoring of mips16 tablegen classes. Make register classesAkira Hatanaka2012-05-311-0/+5
| | | | | | | | | CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16 jalr instruction. Patch by Reed Kotler. llvm-svn: 157730
* Change interface for TargetLowering::LowerCallTo and TargetLowering::LowerCallJustin Holewinski2012-05-251-9/+14
| | | | | | | | | | to pass around a struct instead of a large set of individual values. This cleans up the interface and allows more information to be added to the struct for future targets without requiring changes to each and every target. NV_CONTRIB llvm-svn: 157479
* Make the following changes in MipsISelLowering.cpp:Akira Hatanaka2012-05-121-8/+8
| | | | | | | | | - Stop creating stack frame objects needed for saving $gp. - Insert a node that copies the global pointer register to register $gp before the call node. This will ensure $gp is valid at the entry of the called function. llvm-svn: 156692
* Expand 64-bit shifts if target ABI is O32.Akira Hatanaka2012-05-091-3/+81
| | | | llvm-svn: 156457
* Add support for the 'x' constraint.Eric Christopher2012-05-071-1/+8
| | | | | | Patch by Jack Carter. llvm-svn: 156295
* Add support for the 'l' constraint.Eric Christopher2012-05-071-0/+7
| | | | | | Patch by Jack Carter. llvm-svn: 156294
* Add support for the 'c' constraint.Eric Christopher2012-05-071-1/+13
| | | | | | Patch by Jack Carter. llvm-svn: 156293
* Add support for the 'P' constraint.Eric Christopher2012-05-071-0/+11
| | | | | | Patch by Jack Carter. llvm-svn: 156292
* Add support for the 'O' constraint.Eric Christopher2012-05-071-0/+11
| | | | | | Patch by Jack Carter. llvm-svn: 156285
* Add support for the 'N' inline asm constraint.Eric Christopher2012-05-071-0/+11
| | | | | | Patch by Jack Carter. llvm-svn: 156284
* Add support for the 'L' inline asm constraint.Eric Christopher2012-05-071-0/+11
| | | | | | Patch by Jack Carter. llvm-svn: 156283
* Add support for the inline asm constraint 'K'.Eric Christopher2012-05-071-0/+11
| | | | llvm-svn: 156282
* Support the 'J' constraint.Eric Christopher2012-05-071-0/+11
| | | | | | Patch by Jack Carter. llvm-svn: 156280
* Add support for the 'I' inline asm constraint. Also add testsEric Christopher2012-05-071-0/+39
| | | | | | | | from the previous 2 patches. Patch by Jack Carter. llvm-svn: 156279
* Allow 64 bit integer values in gpu registers if arch and abi are 64 bit.Eric Christopher2012-05-071-2/+4
| | | | | | Patch by Jack Carter. llvm-svn: 156278
* When using inline asm constraints representingEric Christopher2012-05-071-1/+1
| | | | | | | | | non-floating point general registers allow 8 and 16-bit elements. Patch by Jack Carter. llvm-svn: 156277
* Make ARM and Mips use TargetMachine::getTLSModel()Hans Wennborg2012-05-041-3/+6
| | | | | | | | This moves the logic for selecting a TLS model to a single place, instead of the previous three (ARM, Mips, and X86 which already uses this function). llvm-svn: 156162
* llvm/lib/Target: [PR12611] Add "llvm/Support/raw_ostream.h" for Debug build ↵NAKAMURA Takumi2012-04-211-0/+2
| | | | | | | | on MSVC. Thanks to Andy Gibbs, to report the issue. llvm-svn: 155287
* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-19/+19
| | | | | | since they are equivalent. llvm-svn: 155188
* Emit neg.s or neg.d only if -enable-no-nans-fp-math is supplied by user,Akira Hatanaka2012-04-111-0/+5
| | | | | | otherwise expand FNEG during legalization. llvm-svn: 154546
* Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user.Akira Hatanaka2012-04-111-0/+63
| | | | | | Invalid operation is signaled if the operand of these instructions is NaN. llvm-svn: 154545
* Fix bugs in lowering of FCOPYSIGN nodes.Akira Hatanaka2012-04-111-52/+91
| | | | | | | | | | - FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). llvm-svn: 154540
* Reapply 154038 without the failing test.Akira Hatanaka2012-04-041-3/+3
| | | | llvm-svn: 154062
* Revert r154038. It was causing make check failures.Owen Anderson2012-04-041-3/+3
| | | | llvm-svn: 154054
* Fix LowerGlobalAddress to produce instructions with the correct relocationAkira Hatanaka2012-04-041-3/+3
| | | | | | types for N32 ABI. Add new test case and update existing ones. llvm-svn: 154038
* Fix LowerJumpTable to produce instructions with the correct relocationAkira Hatanaka2012-04-041-2/+2
| | | | | | | types for N32 ABI. Test case will be updated after the patch that fixes TargetLowering::getPICJumpTableRelocBase is checked in. llvm-svn: 154036
* Fix LowerConstantPool to produce instructions with the correct relocationAkira Hatanaka2012-04-041-2/+2
| | | | | | types for N32 ABI and update test case. llvm-svn: 154034
* Fix LowerBlockAddress to produce instructions with the correct relocationAkira Hatanaka2012-04-041-2/+2
| | | | | | types for N32 ABI and update test case. llvm-svn: 154031
* Expand FREM.Akira Hatanaka2012-03-291-0/+2
| | | | llvm-svn: 153671
* Pass the llvm IR pointer value and offset to the constructor ofAkira Hatanaka2012-03-271-9/+13
| | | | | | | | | | | | MachinePointerInfo when getStore is called to create a node that stores an argument passed in register to the stack. Without this change, the post RA scheduler will fail to discover the dependencies between the stores instructions and the instructions that load from a structure passed by value. The link to the related discussion is here: http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-March/048055.html llvm-svn: 153499
* Fix bug in LowerConstantPool. Akira Hatanaka2012-03-271-1/+1
| | | | llvm-svn: 153498
* Reorder includes in Target backends to following coding standards. Remove ↵Craig Topper2012-03-171-2/+2
| | | | | | some superfluous forward declarations. llvm-svn: 152997
* Convert more static tables of registers used by calling convention to ↵Craig Topper2012-03-111-10/+10
| | | | | | uint16_t to reduce space. llvm-svn: 152538
* Do not custom lower i64 nodes if i64 is not a legal type. Move lines that setAkira Hatanaka2012-03-101-11/+14
| | | | | | operation action of nodes. llvm-svn: 152452
* Lower SETCC nodes during legalization. Previously, it was lowered in DAG ↵Akira Hatanaka2012-03-091-20/+15
| | | | | | combine pass. llvm-svn: 152450
* Invoke setTargetDAGCombine for SELECT.Akira Hatanaka2012-03-081-0/+1
| | | | llvm-svn: 152290
* Swap the operands of a select node if the false (the second) operand is 0.Akira Hatanaka2012-03-081-0/+35
| | | | | | | | | | | | For example, this pattern (select (setcc lhs, rhs, cc), true, 0) is transformed to this one: (select (setcc lhs, rhs, inverse(cc)), 0, true) This enables MipsDAGToDAGISel::ReplaceUsesWithZeroReg (added in r152280) to replace 0 with $zero. llvm-svn: 152285
* Set minimum function alignment to 3 if target is Mips64.Akira Hatanaka2012-03-081-1/+1
| | | | llvm-svn: 152282
* Changes for migrating to using register mask operands.Akira Hatanaka2012-03-011-0/+6
| | | | llvm-svn: 151847
* Fix bugs which were introduced when support for base+index floating point loadsAkira Hatanaka2012-03-011-1/+0
| | | | | | | | | | | and stores was added. - SelectAddr should return false if Parent is an unaligned f32 load or store. - Only aligned load and store nodes should be matched to select reg+imm floating point instructions. - MIPS does not have support for f64 unaligned load or store instructions. llvm-svn: 151843
* Re-commit r151623 with fix. Only issue special no-return calls if it's a ↵Evan Cheng2012-02-281-2/+4
| | | | | | direct call. llvm-svn: 151645
* Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack ↵Daniel Dunbar2012-02-281-4/+2
| | | | | | prediction. ...", it is breaking the Clang build during the Compiler-RT part. llvm-svn: 151630
* remove blanks, and some code formatJia Liu2012-02-281-39/+39
| | | | llvm-svn: 151625
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