diff options
| author | Akira Hatanaka <ahatanaka@mips.com> | 2012-05-31 02:59:44 +0000 |
|---|---|---|
| committer | Akira Hatanaka <ahatanaka@mips.com> | 2012-05-31 02:59:44 +0000 |
| commit | bff8e31d3cf1335e594f3b6d65cc97dddf31b181 (patch) | |
| tree | de3b2fb8ca840364c2d5ecd5b9c186c2ac0176b3 /llvm/lib/Target/Mips/MipsISelLowering.cpp | |
| parent | 5bcaf5836b3f65f6571c28c6ca9e7933e585254d (diff) | |
| download | bcm5719-llvm-bff8e31d3cf1335e594f3b6d65cc97dddf31b181.tar.gz bcm5719-llvm-bff8e31d3cf1335e594f3b6d65cc97dddf31b181.zip | |
Cleanup and factoring of mips16 tablegen classes. Make register classes
CPU16RegsRegClass and CPURARegRegClass available. Add definition of mips16
jalr instruction.
Patch by Reed Kotler.
llvm-svn: 157730
Diffstat (limited to 'llvm/lib/Target/Mips/MipsISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsISelLowering.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 7335858e079..6ea2692d6f8 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -103,6 +103,11 @@ MipsTargetLowering(MipsTargetMachine &TM) if (HasMips64) addRegisterClass(MVT::i64, &Mips::CPU64RegsRegClass); + if (Subtarget->inMips16Mode()) { + addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); + addRegisterClass(MVT::i32, &Mips::CPURARegRegClass); + } + if (!TM.Options.UseSoftFloat) { addRegisterClass(MVT::f32, &Mips::FGR32RegClass); |
