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| author | Eric Christopher <echristo@apple.com> | 2012-05-07 03:13:16 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@apple.com> | 2012-05-07 03:13:16 +0000 |
| commit | cfcd77b0bc7133371217578867841622b00afe17 (patch) | |
| tree | 131d7a8096a47a83a13363a9a4c80402aa9e27ad /llvm/lib/Target/Mips/MipsISelLowering.cpp | |
| parent | b51ffd762ca41878ab375a17383e4ef001b0c452 (diff) | |
| download | bcm5719-llvm-cfcd77b0bc7133371217578867841622b00afe17.tar.gz bcm5719-llvm-cfcd77b0bc7133371217578867841622b00afe17.zip | |
When using inline asm constraints representing
non-floating point general registers allow 8 and 16-bit
elements.
Patch by Jack Carter.
llvm-svn: 156277
Diffstat (limited to 'llvm/lib/Target/Mips/MipsISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index fc03ac55ae1..bb36d76ab75 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -3054,7 +3054,7 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const case 'd': // Address register. Same as 'r' unless generating MIPS16 code. case 'y': // Same as 'r'. Exists for compatibility. case 'r': - if (VT == MVT::i32) + if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) return std::make_pair(0U, &Mips::CPURegsRegClass); assert(VT == MVT::i64 && "Unexpected type."); return std::make_pair(0U, &Mips::CPU64RegsRegClass); |
