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| author | Eric Christopher <echristo@apple.com> | 2012-05-07 03:13:22 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@apple.com> | 2012-05-07 03:13:22 +0000 |
| commit | 58daf0468137646063d07b850d2654c3e7f63792 (patch) | |
| tree | cb06734ef1f4280711b5b701d7ad50f82ac03e35 /llvm/lib/Target/Mips/MipsISelLowering.cpp | |
| parent | cfcd77b0bc7133371217578867841622b00afe17 (diff) | |
| download | bcm5719-llvm-58daf0468137646063d07b850d2654c3e7f63792.tar.gz bcm5719-llvm-58daf0468137646063d07b850d2654c3e7f63792.zip | |
Allow 64 bit integer values in gpu registers if arch and abi are 64 bit.
Patch by Jack Carter.
llvm-svn: 156278
Diffstat (limited to 'llvm/lib/Target/Mips/MipsISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/MipsISelLowering.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index bb36d76ab75..be22fed2f45 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -3056,8 +3056,10 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const case 'r': if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8) return std::make_pair(0U, &Mips::CPURegsRegClass); - assert(VT == MVT::i64 && "Unexpected type."); - return std::make_pair(0U, &Mips::CPU64RegsRegClass); + if (VT == MVT::i64 && HasMips64) + return std::make_pair(0U, &Mips::CPU64RegsRegClass); + // This will generate an error message + return std::make_pair(0u, static_cast<const TargetRegisterClass*>(0)); case 'f': if (VT == MVT::f32) return std::make_pair(0U, &Mips::FGR32RegClass); |
