summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
Commit message (Collapse)AuthorAgeFilesLines
* Silencing two MSVC warnings; 'argument' : truncation from 'unsigned int' to ↵Aaron Ballman2015-07-141-1/+1
| | | | | | 'int16_t' and truncation of constant value. NFC intended. llvm-svn: 242145
* [mips] Fix li/la differences between IAS and GAS.Daniel Sanders2015-07-141-82/+83
| | | | | | | | | | | | | | | | | | | Summary: - Signed 16-bit should have priority over unsigned. - For la, unsigned 16-bit must use ori+addu rather than directly use ori. - Correct tests on 32-bit immediates with 64-bit predicates by sign-extending the immediate beforehand. For example, isInt<16>(0xffff8000) should be true and use addiu. Also split li/la testing into separate files due to their size. Reviewers: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10967 llvm-svn: 242139
* [mips] [IAS] Add support for the .module softfloat/hardfloat directives.Toma Tabacu2015-06-301-0/+40
| | | | | | | | | These directives are used to set the default value of the SoftFloat feature. They have the same effect as setting -m{soft, hard}-float from the command line. Differential Revision: http://reviews.llvm.org/D9073 llvm-svn: 241066
* [mips] [IAS] Make .module directives change AssemblerOptions->front().Toma Tabacu2015-06-301-8/+34
| | | | | | Differential Revision: http://reviews.llvm.org/D10643 llvm-svn: 241062
* Reverting r241058 because it's causing buildbot failures.Ranjeet Singh2015-06-301-3/+1
| | | | llvm-svn: 241061
* There are a few places where subtarget features are stillRanjeet Singh2015-06-301-1/+3
| | | | | | | | | represented by uint64_t, this patch replaces these usages with the FeatureBitset (std::bitset) type. Differential Revision: http://reviews.llvm.org/D10542 llvm-svn: 241058
* [mips] [IAS] Add support for the .set oddspreg/nooddspreg directives.Toma Tabacu2015-06-301-0/+34
| | | | | | Differential Revision: http://reviews.llvm.org/D10657 llvm-svn: 241052
* [mips] Add COP0 register class and use it in M[FT]C0/DM[FT]C0.Daniel Sanders2015-06-271-2/+18
| | | | | | | | | | | | | | | | | Summary: Previously it (incorrectly) used GPR's. Patch by Simon Dardis. A couple small corrections by myself. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10567 llvm-svn: 240883
* [mips] [IAS] Add partial support for the ULW pseudo-instruction.Toma Tabacu2015-06-261-0/+79
| | | | | | | | | | | | | | | | Summary: This only adds support for ULW of an immediate address with/without a source register. It does not include support for ULW of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9663 llvm-svn: 240782
* [mips] [IAS] Refactor the emitDirectiveModuleFP() functions. NFC.Toma Tabacu2015-06-251-3/+17
| | | | | | | | | | | | | | | | | | | | Summary: Simplify emitDirectiveModuleFP() by having it just print the current information from MipsABIFlagsSection and doing an updateABIInfo() before such calls. This prevents us from forgetting to update the STI.FeatureBits, because updateABIInfo() uses those to update the MipsABIFlagsSection object, and also makes sure we use the update mechanism from MipsABIFlagsSection. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D10642 llvm-svn: 240637
* [mips] [IAS] Refactor the emitDirectiveModuleOddSPReg() functions. NFC.Toma Tabacu2015-06-251-2/+18
| | | | | | | | | | | | | | | | | | | Summary: We can simplify emitDirectiveModuleOddSPReg() by having it print the current OddSPReg information from MipsABIFlagsSection and doing an updateABIInfo() before such calls. This prevents us from forgetting to update the STI.FeatureBits, because updateABIInfo() uses those to update the MipsABIFlagsSection object, and also makes sure we use the update mechanism from MipsABIFlagsSection. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D10641 llvm-svn: 240630
* [mips] [IAS] Fix parsing of memory offset expressions with parenthesis depth >1.Toma Tabacu2015-06-251-2/+5
| | | | | | | | | | | | | | | | | | | Summary: In an expression such as "(((a+b)+c)+d)", parseParenExpression() would only parse the "a+b)+c", which would result in an error later on in the parser. This means that we can only parse one level of inner parentheses. In order to fix this, I added a new function called parseParenExprOfDepth(), which parses a specified number of trailing parenthesis expressions (except for the outermost parenthesis), and changed MipsAsmParser to use it in parseMemOffset instead of parseParenExpression(). Reviewers: dsanders, rafael Reviewed By: dsanders, rafael Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9742 llvm-svn: 240625
* [mips] [IAS] Add partial support for the ULHU pseudo-instruction.Toma Tabacu2015-06-231-0/+111
| | | | | | | | | | | | | | | | Summary: This only adds support for ULHU of an immediate address with/without a source register. It does not include support for ULHU of the address of a symbol. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9671 llvm-svn: 240410
* [mips] [IAS] Add support for generating DADDu to createAddu(). NFC.Toma Tabacu2015-06-231-7/+7
| | | | | | | | | | | | | | Summary: This isn't used right now, but it will be in some upcoming changes. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10568 llvm-svn: 240407
* [mips] [IAS] Add support for LAReg with identical source and destination ↵Toma Tabacu2015-06-221-15/+25
| | | | | | | | | | | | | | | | register operands. Summary: In this case, we're supposed to load the immediate in AT and then ADDu it with the source register and put it in the destination register. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9367 llvm-svn: 240278
* [mips] [IAS] Add support for LASym with identical source and destination ↵Toma Tabacu2015-06-221-8/+20
| | | | | | | | | | | | | | | | | | register operands. Summary: In this case, we're supposed to load the address of the symbol in AT and then ADDu it with the source register and put it in the destination register. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9366 llvm-svn: 240273
* [mips] [IAS] Add support for expanding LASym with a source register operand.Toma Tabacu2015-06-171-12/+19
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9348 llvm-svn: 239910
* [mips] [IAS] Add support for the B{L,G}{T,E}(U) branch pseudo-instructions.Toma Tabacu2015-06-171-0/+220
| | | | | | | | | | | | | | | | Summary: This does not include support for the immediate variants of these pseudo-instructions. Fixes llvm.org/PR20968. Reviewers: dsanders Reviewed By: dsanders Subscribers: seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D8537 llvm-svn: 239905
* [mips] [IAS] Fix LA with relative label operands.Toma Tabacu2015-06-171-12/+9
| | | | | | | | | | | | | | | | | Summary: Call MCSymbolRefExpr::create() with a MCSymbol* argument, not with a StringRef of the Symbol's name, in order to avoid creating invalid temporary symbols for relative labels (e.g. {$,.L}tmp00, {$,.L}tmp10 etc.). Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D10498 llvm-svn: 239901
* [mips] [IAS] Fix LW with relative label operands.Toma Tabacu2015-06-171-21/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Previously, MCSymbolRefExpr::create() was called with a StringRef of the symbol name, which it would then search for in the Symbols StringMap (from MCContext). However, relative labels (which are temporary symbols) are apparently not stored in the Symbols StringMap, so we end up creating a new {$,.L}tmp symbol ({$,.L}tmp00, {$,.L}tmp10 etc.) each time we create an MCSymbolRefExpr by passing in the symbol name as a StringRef. Fortunately, there is a version of MCSymbolRefExpr::create() which takes an MCSymbol* and we already have an MCSymbol* at that point, so we can just pass that in instead of the StringRef. I also removed the local StringRef calls to MCSymbolRefExpr::create() from expandMemInst(), as those cases can be handled by evaluateRelocExpr() anyway. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9938 llvm-svn: 239897
* [mips] [IAS] Refactor symbol-address loading code into a helper function. NFC.Toma Tabacu2015-06-161-17/+23
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9523 llvm-svn: 239811
* Recommit "[mips] [IAS] Add support for BNE and BEQ with an immediate ↵Toma Tabacu2015-06-111-0/+61
| | | | | | | | | operand." (r239396). Apparently, Arcanist didn't include some of my local changes in my previous commit attempt. llvm-svn: 239523
* [mips] Change existing uimm10 operand to restrict the accepted immediatesZoran Jovanovic2015-06-111-0/+3
| | | | | | http://reviews.llvm.org/D10312 llvm-svn: 239520
* Recommit "[mips] [IAS] Restore STI.FeatureBits in .set pop." (r239144).Toma Tabacu2015-06-091-11/+15
| | | | | | | Specified the llvm namespace for the 2 calls to make_unique() which caused compilation errors in Visual Studio 2013. llvm-svn: 239405
* Revert "[mips] [IAS] Add support for BNE and BEQ with an immediate operand." ↵Toma Tabacu2015-06-091-61/+0
| | | | | | | | (r239396). It was breaking buildbots. llvm-svn: 239397
* [mips] [IAS] Add support for BNE and BEQ with an immediate operand.Toma Tabacu2015-06-091-0/+61
| | | | | | | | | | | | | | | | Summary: For some branches, GAS accepts an immediate instead of the 2nd register operand. We only implement this for BNE and BEQ for now. Other branch instructions can be added later, if needed. Reviewers: dsanders Reviewed By: dsanders Subscribers: seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D9666 llvm-svn: 239396
* Revert "[mips] [IAS] Restore STI.FeatureBits in .set pop." (r239144).Toma Tabacu2015-06-051-15/+11
| | | | | | This is breaking the Windows buildbots. llvm-svn: 239145
* [mips] [IAS] Restore STI.FeatureBits in .set pop.Toma Tabacu2015-06-051-11/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Only restoring AvailableFeatures is not enough and will lead to buggy behaviour. For example, if we have a feature enabled and we ".set pop", the next time we try to ".set" that feature nothing will happen because the "!(STI.getFeatureBits()[Feature])" check will be false, because we didn't restore STI.FeatureBits. In order to fix this, we need to make MipsAssemblerOptions remember the STI.FeatureBits instead of the AvailableFeatures and then regenerate AvailableFeatures each time we ".set pop". This is because, AFAIK, there is no way to convert from AvailableFeatures back to STI.FeatureBits, but the reverse is possible by using ComputeAvailableFeatures(STI.FeatureBits). I also moved the updating of AssemblerOptions inside the "if" statement in setFeatureBits() and clearFeatureBits(), as there is no reason to update if nothing changes. Reviewers: dsanders, mkuper Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9156 llvm-svn: 239144
* [mips] [IAS] Add support for the .set softfloat/hardfloat directives.Toma Tabacu2015-06-021-0/+28
| | | | | | | | | | | | | | Summary: These directives are used to set the current value of the SoftFloat feature. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D9074 llvm-svn: 238813
* MC: Clean up MCExpr naming. NFC.Jim Grosbach2015-05-301-22/+22
| | | | llvm-svn: 238634
* Use operator<< instead of print in a few more places.Rafael Espindola2015-05-271-2/+2
| | | | llvm-svn: 238315
* Use std::bitset for SubtargetFeatures.Michael Kuperstein2015-05-261-38/+42
| | | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures. Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. This should now be fixed. llvm-svn: 238192
* [mips] [IAS] Factor out .set nomacro warning. NFC.Toma Tabacu2015-05-201-8/+11
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9772 llvm-svn: 237780
* MC: Clean up method names in MCContext.Jim Grosbach2015-05-181-4/+4
| | | | | | | The naming was a mish-mash of old and new style. Update to be consistent with the new. NFC. llvm-svn: 237594
* [mips] [IAS] Fix expansion of negative 32-bit immediates for LI/DLI.Toma Tabacu2015-05-151-5/+18
| | | | | | | | | | | | | | | | | | Summary: To maintain compatibility with GAS, we need to stop treating negative 32-bit immediates as 64-bit values when expanding LI/DLI. This currently happens because of sign extension. To do this we need to choose the 32-bit value expansion for values which use their upper 33 bits only for sign extension (i.e. no 0's, only 1's). Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8662 llvm-svn: 237428
* [mips] [IAS] Enforce .set nomacro.Toma Tabacu2015-05-141-0/+10
| | | | | | | | | | | | | | Summary: When used, ".set nomacro" causes warning messages to be reported when we expand pseudo-instructions to multiple machine instructions. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9564 llvm-svn: 237366
* [mips] [IAS] Emit .set macro/nomacro.Toma Tabacu2015-05-141-0/+2
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9563 llvm-svn: 237363
* [mips] [IAS] Warn when LA is used with a 64-bit symbol.Toma Tabacu2015-05-141-8/+11
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9295 llvm-svn: 237356
* [mips] [IAS] Give expandLoadAddressSym() more specific arguments. NFC.Toma Tabacu2015-05-141-23/+13
| | | | | | | | | | | | | | | | Summary: If we only pass the necessary operands, we don't have to determine the position of the symbol operand when entering expandLoadAddressSym(). This simplifies the expandLoadAddressSym() code. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9291 llvm-svn: 237355
* MC: Modernize MCOperand API naming. NFC.Jim Grosbach2015-05-131-90/+90
| | | | | | MCOperand::Create*() methods renamed to MCOperand::create*(). llvm-svn: 237275
* [mips] [IAS] Preemptively fix warning introduced by r237255. NFC.Toma Tabacu2015-05-131-3/+6
| | | | | | | | | | | Some compilers warn about using the ternary operator with an unsigned variable and enum. I haven't seen this trigger in the llvm.org buildbots yet, but it probably will at some point. Reported by Daniel Sanders. llvm-svn: 237262
* [mips] [IAS] Unify common functionality of LA and LI.Toma Tabacu2015-05-131-86/+82
| | | | | | | | | | | | | | Summary: A side-effect of this is that LA gains proper handling of unsigned and positive signed 16-bit immediates and more accurate error messages. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9290 llvm-svn: 237255
* Reverting r237234, "Use std::bitset for SubtargetFeatures"Michael Kuperstein2015-05-131-42/+38
| | | | | | | The buildbots are still not satisfied. MIPS and ARM are failing (even though at least MIPS was expected to pass). llvm-svn: 237245
* Use std::bitset for SubtargetFeaturesMichael Kuperstein2015-05-131-38/+42
| | | | | | | | | | | Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first two times this was committed (r229831, r233055), it caused several buildbot failures. At least some of the ARM and MIPS ones were due to gcc/binutils issues, and should now be fixed. llvm-svn: 237234
* Rename the MIPS routine abiUsesSoftFloat -> useSoftFloat to matchEric Christopher2015-05-071-1/+1
| | | | | | some incoming changes and the general scheme used by features (use/has). llvm-svn: 236794
* [mips] Add the SoftFloat MipsSubtarget feature.Toma Tabacu2015-05-071-2/+4
| | | | | | | | | | | | | | Summary: This will enable the IAS to reject floating point instructions if soft-float is enabled. Reviewers: dsanders, echristo Reviewed By: dsanders Subscribers: jfb, llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D9053 llvm-svn: 236713
* [mips] [IAS] Fix error messages for using LI with 64-bit immediates.Toma Tabacu2015-05-011-12/+13
| | | | | | | | | | | | | | | | Summary: LI should never accept immediates larger than 32 bits. The additional Is32BitImm boolean also paves the way for unifying the functionality that LA and LI have in common. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9289 llvm-svn: 236313
* [mips] [IAS] Slightly improve shift instruction generation in expandLoadImm.Toma Tabacu2015-05-011-20/+35
| | | | | | | | | | | | | | | | | | | Summary: Generate one DSLL32 of 0 instead of two consecutive DSLL of 16. In order to do this I had to change createLShiftOri's template argument from a bool to an unsigned. This also gave me the opportunity to rewrite the mips64-expansions.s test, as it was testing the same cases multiple times and skipping over other cases. It was also somewhat unreadable, as the CHECK lines were grouped in a huge block of text at the beginning of the file. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8974 llvm-svn: 236311
* [mips] [IAS] Inline assemble-time shifting out of createLShiftOri. NFC.Toma Tabacu2015-04-291-15/+24
| | | | | | | | | | | | | | | | Summary: Do the assemble-time shifts from createLShiftOri at the source, which groups all the shifting together, closer to the main logic path, and store the results in concisely-named variables to improve code clarity. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8973 llvm-svn: 236096
* [mips] [IAS] Do not generate redundant ORi in createLShiftOri.Toma Tabacu2015-04-281-0/+4
| | | | | | | | | | | | | | Summary: If the immediate is 0, the ORi is pointless. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8969 llvm-svn: 235990
OpenPOWER on IntegriCloud