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| author | Toma Tabacu <toma.tabacu@imgtec.com> | 2015-06-23 14:00:54 +0000 |
|---|---|---|
| committer | Toma Tabacu <toma.tabacu@imgtec.com> | 2015-06-23 14:00:54 +0000 |
| commit | 0b3e97874d4d8d759a26c07ba7c45e544a0a4726 (patch) | |
| tree | d6a6f417a2fa70262045e45b9e635f468602d30d /llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | |
| parent | b633d20d3644e93434b39accac04a86f4b16bfcd (diff) | |
| download | bcm5719-llvm-0b3e97874d4d8d759a26c07ba7c45e544a0a4726.tar.gz bcm5719-llvm-0b3e97874d4d8d759a26c07ba7c45e544a0a4726.zip | |
[mips] [IAS] Add support for generating DADDu to createAddu(). NFC.
Summary: This isn't used right now, but it will be in some upcoming changes.
Reviewers: dsanders
Reviewed By: dsanders
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D10568
llvm-svn: 240407
Diffstat (limited to 'llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp')
| -rw-r--r-- | llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index 3cb53cb568a..1cf3b5e3c91 100644 --- a/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -218,7 +218,7 @@ class MipsAsmParser : public MCTargetAsmParser { SmallVectorImpl<MCInst> &Instructions); void createAddu(unsigned DstReg, unsigned SrcReg, unsigned TrgReg, - SmallVectorImpl<MCInst> &Instructions); + bool Is64Bit, SmallVectorImpl<MCInst> &Instructions); bool reportParseError(Twine ErrorMsg); bool reportParseError(SMLoc Loc, Twine ErrorMsg); @@ -1836,7 +1836,7 @@ bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg, createLShiftOri<0>(Bits15To0, TmpReg, IDLoc, Instructions); if (UseSrcReg) - createAddu(DstReg, TmpReg, SrcReg, Instructions); + createAddu(DstReg, TmpReg, SrcReg, !Is32BitImm, Instructions); } else if ((ImmValue & (0xffffLL << 48)) == 0) { if (Is32BitImm) { @@ -1870,7 +1870,7 @@ bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg, createLShiftOri<16>(Bits15To0, TmpReg, IDLoc, Instructions); if (UseSrcReg) - createAddu(DstReg, TmpReg, SrcReg, Instructions); + createAddu(DstReg, TmpReg, SrcReg, !Is32BitImm, Instructions); } else { if (Is32BitImm) { @@ -1914,7 +1914,7 @@ bool MipsAsmParser::loadImmediate(int64_t ImmValue, unsigned DstReg, } if (UseSrcReg) - createAddu(DstReg, TmpReg, SrcReg, Instructions); + createAddu(DstReg, TmpReg, SrcReg, !Is32BitImm, Instructions); } return false; } @@ -2051,7 +2051,7 @@ bool MipsAsmParser::loadAndAddSymbolAddress( } if (UseSrcReg) - createAddu(DstReg, TmpReg, SrcReg, Instructions); + createAddu(DstReg, TmpReg, SrcReg, !Is32BitSym, Instructions); return false; } @@ -2488,10 +2488,10 @@ void MipsAsmParser::createNop(bool hasShortDelaySlot, SMLoc IDLoc, } void MipsAsmParser::createAddu(unsigned DstReg, unsigned SrcReg, - unsigned TrgReg, + unsigned TrgReg, bool Is64Bit, SmallVectorImpl<MCInst> &Instructions) { MCInst AdduInst; - AdduInst.setOpcode(Mips::ADDu); + AdduInst.setOpcode(Is64Bit ? Mips::DADDu : Mips::ADDu); AdduInst.addOperand(MCOperand::createReg(DstReg)); AdduInst.addOperand(MCOperand::createReg(SrcReg)); AdduInst.addOperand(MCOperand::createReg(TrgReg)); |
