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path: root/llvm/lib/Target/Hexagon/HexagonPatterns.td
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* Fix pattern error for S2_tstbit_i instructionIkhlas Ajbar2019-10-301-2/+2
* [Hexagon] Bitcast v4i16 to v8i8, unify no-op casts between scalar and HVXKrzysztof Parzyszek2019-09-231-11/+19
* DAG/GlobalISel: Correct type profile of bitcount opsMatt Arsenault2019-09-131-4/+4
* [Hexagon] Improve generated code for test-if-bit-clear, one more timeKrzysztof Parzyszek2019-09-041-18/+29
* [Hexagon] Improve generated code for test-if-bit-clearKrzysztof Parzyszek2019-08-261-0/+22
* [Hexagon] Generate min/max instructions for 64-bit vectorsKrzysztof Parzyszek2019-08-161-24/+65
* [Hexagon] Fix instruction selection for vselect v4i8Krzysztof Parzyszek2019-08-151-8/+0
* Change some dyn_cast to more apropriate isa. NFCFangrui Song2019-04-051-1/+1
* [Hexagon] Use misaligned load instead of trap0(#0) for __builtin_trapKrzysztof Parzyszek2019-02-211-1/+1
* Revert r354606, it breaks asan testsKrzysztof Parzyszek2019-02-211-1/+1
* [Hexagon] Use misaligned load instead of trap0(#0) for __builtin_trapKrzysztof Parzyszek2019-02-211-1/+1
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [Hexagon] Add patterns for funnel shiftsKrzysztof Parzyszek2018-12-201-1/+87
* [Hexagon] Add patterns for shifts of v2i16Krzysztof Parzyszek2018-12-141-0/+12
* [Hexagon] Use IMPLICIT_DEF to any-extend 32-bit values to 64 bitsKrzysztof Parzyszek2018-12-141-23/+25
* [Hexagon] Add patterns for any_extend from i1 and short vectors of i1Krzysztof Parzyszek2018-12-101-29/+28
* [Hexagon] Add instruction definitions for Hexagon V66Krzysztof Parzyszek2018-12-051-0/+7
* [Hexagon] Remove support for V4Krzysztof Parzyszek2018-10-191-123/+103
* [Hexagon] Restrict compound instructions with constant value.Sumanth Gundapaneni2018-10-111-10/+27
* [Hexagon] Remove incorrect pattern for swizKrzysztof Parzyszek2018-10-011-8/+0
* [Hexagon] Map ISD::TRAP to J2_trap0(#0)Krzysztof Parzyszek2018-08-091-0/+2
* [Hexagon] Diagnose misaligned absolute loads and storesKrzysztof Parzyszek2018-08-081-70/+135
* [TableGen] Support multi-alternative pattern fragmentsUlrich Weigand2018-07-131-3/+3
* [Hexagon] Remove 'T' from HasVNN predicates, NFCKrzysztof Parzyszek2018-06-201-16/+16
* [DAGCombiner] Recognize more patterns for ABSKrzysztof Parzyszek2018-06-121-16/+0
* [SelectionDAG] Provide default expansion for rotatesKrzysztof Parzyszek2018-06-121-0/+19
* [Hexagon] Add pattern to generate 64-bit neg instructionKrzysztof Parzyszek2018-06-051-4/+5
* [Hexagon] Add more patterns for generating abs/absp instructionsKrzysztof Parzyszek2018-06-051-5/+15
* [Hexagon] Add patterns for accumulating HVX comparesKrzysztof Parzyszek2018-05-221-49/+49
* [Hexagon] Add a target feature for memop generationKrzysztof Parzyszek2018-05-141-4/+8
* [Hexagon] Avoid predicate copies to integer registers from store-lockedKrzysztof Parzyszek2018-05-141-0/+15
* [Hexagon] Add/fix patterns for 32/64-bit vector compares and logical opsKrzysztof Parzyszek2018-04-191-52/+41
* [Hexagon] Fix zero-extending non-HVX bool vectorsKrzysztof Parzyszek2018-03-161-11/+19
* [Hexagon] Rewrite non-HVX unaligned loads as pairs of aligned onesKrzysztof Parzyszek2018-03-071-45/+86
* [Hexagon] Add patterns for compares of i1 valuesKrzysztof Parzyszek2018-02-271-2/+4
* [DAGCOmbine] Ensure that (brcond (setcc ...)) is handled in a canonical manner.Amaury Sechet2018-02-231-0/+2
* [Hexagon] Split HVX vector pair loads/stores, expand unaligned loadsKrzysztof Parzyszek2018-02-141-27/+0
* [Hexagon] Extract HVX lowering and selection into HVX-specific files, NFCKrzysztof Parzyszek2018-02-061-339/+0
* [Hexagon] Split HVX operations on vector pairsKrzysztof Parzyszek2018-02-061-14/+82
* [Hexagon] Handle lowering of SETCC via setCondCodeActionKrzysztof Parzyszek2018-02-061-2/+41
* [Hexagon] Implement HVX codegen for vector shiftsKrzysztof Parzyszek2018-01-311-4/+18
* [Hexagon] Generate constant splats instead of loads from constant poolKrzysztof Parzyszek2018-01-261-0/+21
* [Hexagon] Remove unused HexagonISD opcodes, NFCKrzysztof Parzyszek2018-01-241-13/+0
* [Hexagon] Add patterns for sext_inreg of HVX vector typesKrzysztof Parzyszek2018-01-231-0/+19
* [Hexagon] Implement basic vector operations on vectors vNi1Krzysztof Parzyszek2018-01-231-18/+60
* [Hexagon] Implement signed and unsigned multiply-high for vectorsKrzysztof Parzyszek2018-01-151-0/+50
* [Hexagon] Even simpler patterns for sign- and zero-extending HVX vectorsKrzysztof Parzyszek2018-01-051-16/+4
* Revert r321894: it requires a part of another commit that is not ready yetKrzysztof Parzyszek2018-01-051-19/+0
* Revert r321897: affected testcases were not updatedKrzysztof Parzyszek2018-01-051-4/+16
* [Hexagon] Even simpler patterns for sign- and zero-extending HVX vectorsKrzysztof Parzyszek2018-01-051-16/+4
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