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path: root/llvm/lib/Target/Hexagon/HexagonPatterns.td
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* Fix pattern error for S2_tstbit_i instructionIkhlas Ajbar2019-10-301-2/+2
| | | | | It used to generate S2_tstbit_i with constant -33 which resulted in an assert. The reason is log2_32 was called with 64bit value 0.
* [Hexagon] Bitcast v4i16 to v8i8, unify no-op casts between scalar and HVXKrzysztof Parzyszek2019-09-231-11/+19
| | | | llvm-svn: 372616
* DAG/GlobalISel: Correct type profile of bitcount opsMatt Arsenault2019-09-131-4/+4
| | | | | | | | The result integer does not need to be the same width as the input. AMDGPU, NVPTX, and Hexagon all have patterns working around the types matching. GlobalISel defines these as being different type indexes. llvm-svn: 371797
* [Hexagon] Improve generated code for test-if-bit-clear, one more timeKrzysztof Parzyszek2019-09-041-18/+29
| | | | | | Adjust isel patterns after recent commit. Fixes https://llvm.org/PR43194. llvm-svn: 370913
* [Hexagon] Improve generated code for test-if-bit-clearKrzysztof Parzyszek2019-08-261-0/+22
| | | | llvm-svn: 369947
* [Hexagon] Generate min/max instructions for 64-bit vectorsKrzysztof Parzyszek2019-08-161-24/+65
| | | | llvm-svn: 369124
* [Hexagon] Fix instruction selection for vselect v4i8Krzysztof Parzyszek2019-08-151-8/+0
| | | | llvm-svn: 369040
* Change some dyn_cast to more apropriate isa. NFCFangrui Song2019-04-051-1/+1
| | | | llvm-svn: 357773
* [Hexagon] Use misaligned load instead of trap0(#0) for __builtin_trapKrzysztof Parzyszek2019-02-211-1/+1
| | | | | | | | | The trap instruction is intercepted by various runtime environments, and instead of a crash it creates confusion. This reapplies r354606 with a fix. llvm-svn: 354611
* Revert r354606, it breaks asan testsKrzysztof Parzyszek2019-02-211-1/+1
| | | | llvm-svn: 354609
* [Hexagon] Use misaligned load instead of trap0(#0) for __builtin_trapKrzysztof Parzyszek2019-02-211-1/+1
| | | | | | | The trap instruction is intercepted by various runtime environments, and instead of a crash it creates confusion. llvm-svn: 354606
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [Hexagon] Add patterns for funnel shiftsKrzysztof Parzyszek2018-12-201-1/+87
| | | | llvm-svn: 349770
* [Hexagon] Add patterns for shifts of v2i16Krzysztof Parzyszek2018-12-141-0/+12
| | | | | | This fixes https://llvm.org/PR39983. llvm-svn: 349202
* [Hexagon] Use IMPLICIT_DEF to any-extend 32-bit values to 64 bitsKrzysztof Parzyszek2018-12-141-23/+25
| | | | llvm-svn: 349199
* [Hexagon] Add patterns for any_extend from i1 and short vectors of i1Krzysztof Parzyszek2018-12-101-29/+28
| | | | llvm-svn: 348785
* [Hexagon] Add instruction definitions for Hexagon V66Krzysztof Parzyszek2018-12-051-0/+7
| | | | llvm-svn: 348411
* [Hexagon] Remove support for V4Krzysztof Parzyszek2018-10-191-123/+103
| | | | llvm-svn: 344791
* [Hexagon] Restrict compound instructions with constant value.Sumanth Gundapaneni2018-10-111-10/+27
| | | | | | | | | | Having a constant value operand in the compound instruction is not always profitable. This patch improves coremark by ~4% on Hexagon. Differential Revision: https://reviews.llvm.org/D53152 llvm-svn: 344284
* [Hexagon] Remove incorrect pattern for swizKrzysztof Parzyszek2018-10-011-8/+0
| | | | | | | | | | | | The pattern had a couple of problems: - It was checking for loads of bytes in the reverse order to what it should have been looking for. - It would replace loads of bytes with a load of a word without making sure that the alignment was correct. Thanks to Eli Friedman for pointing it out. llvm-svn: 343514
* [Hexagon] Map ISD::TRAP to J2_trap0(#0)Krzysztof Parzyszek2018-08-091-0/+2
| | | | llvm-svn: 339365
* [Hexagon] Diagnose misaligned absolute loads and storesKrzysztof Parzyszek2018-08-081-70/+135
| | | | | | Differential Revision: https://reviews.llvm.org/D50405 llvm-svn: 339272
* [TableGen] Support multi-alternative pattern fragmentsUlrich Weigand2018-07-131-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A TableGen instruction record usually contains a DAG pattern that will describe the SelectionDAG operation that can be implemented by this instruction. However, there will be cases where several different DAG patterns can all be implemented by the same instruction. The way to represent this today is to write additional patterns in the Pattern (or usually Pat) class that map those extra DAG patterns to the instruction. This usually also works fine. However, I've noticed cases where the current setup seems to require quite a bit of extra (and duplicated) text in the target .td files. For example, in the SystemZ back-end, there are quite a number of instructions that can implement an "add-with-overflow" operation. The same instructions also need to be used to implement just plain addition (simply ignoring the extra overflow output). The current solution requires creating extra Pat pattern for every instruction, duplicating the information about which particular add operands map best to which particular instruction. This patch enhances TableGen to support a new PatFrags class, which can be used to encapsulate multiple alternative patterns that may all match to the same instruction. It operates the same way as the existing PatFrag class, except that it accepts a list of DAG patterns to match instead of just a single one. As an example, we can now define a PatFrags to match either an "add-with-overflow" or a regular add operation: def z_sadd : PatFrags<(ops node:$src1, node:$src2), [(z_saddo node:$src1, node:$src2), (add node:$src1, node:$src2)]>; and then use this in the add instruction pattern: defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>; These SystemZ target changes are implemented here as well. Note that PatFrag is now defined as a subclass of PatFrags, which means that some users of internals of PatFrag need to be updated. (E.g. instead of using PatFrag.Fragment you now need to use !head(PatFrag.Fragments).) The implementation is based on the following main ideas: - InlinePatternFragments may now replace each original pattern with several result patterns, not just one. - parseInstructionPattern delays calling InlinePatternFragments and InferAllTypes. Instead, it extracts a single DAG match pattern from the main instruction pattern. - Processing of the DAG match pattern part of the main instruction pattern now shares most code with processing match patterns from the Pattern class. - Direct use of main instruction patterns in InferFromPattern and EmitResultInstructionAsOperand is removed; everything now operates solely on DAG match patterns. Reviewed by: hfinkel Differential Revision: https://reviews.llvm.org/D48545 llvm-svn: 336999
* [Hexagon] Remove 'T' from HasVNN predicates, NFCKrzysztof Parzyszek2018-06-201-16/+16
| | | | | | Patch by Sumanth Gundapaneni. llvm-svn: 335124
* [DAGCombiner] Recognize more patterns for ABSKrzysztof Parzyszek2018-06-121-16/+0
| | | | | | Differential Revision: https://reviews.llvm.org/D47831 llvm-svn: 334553
* [SelectionDAG] Provide default expansion for rotatesKrzysztof Parzyszek2018-06-121-0/+19
| | | | | | | | | | | | | Implement default legalization of rotates: either in terms of the rotation in the opposite direction (if legal), or in terms of shifts and ors. Implement generating of rotate instructions for Hexagon. Hexagon only supports rotates by an immediate value, so implement custom lowering of ROTL/ROTR on Hexagon. If a rotate is not legal, use the default expansion. Differential Revision: https://reviews.llvm.org/D47725 llvm-svn: 334497
* [Hexagon] Add pattern to generate 64-bit neg instructionKrzysztof Parzyszek2018-06-051-4/+5
| | | | llvm-svn: 334043
* [Hexagon] Add more patterns for generating abs/absp instructionsKrzysztof Parzyszek2018-06-051-5/+15
| | | | llvm-svn: 334038
* [Hexagon] Add patterns for accumulating HVX comparesKrzysztof Parzyszek2018-05-221-49/+49
| | | | llvm-svn: 333009
* [Hexagon] Add a target feature for memop generationKrzysztof Parzyszek2018-05-141-4/+8
| | | | llvm-svn: 332285
* [Hexagon] Avoid predicate copies to integer registers from store-lockedKrzysztof Parzyszek2018-05-141-0/+15
| | | | llvm-svn: 332260
* [Hexagon] Add/fix patterns for 32/64-bit vector compares and logical opsKrzysztof Parzyszek2018-04-191-52/+41
| | | | llvm-svn: 330330
* [Hexagon] Fix zero-extending non-HVX bool vectorsKrzysztof Parzyszek2018-03-161-11/+19
| | | | llvm-svn: 327712
* [Hexagon] Rewrite non-HVX unaligned loads as pairs of aligned onesKrzysztof Parzyszek2018-03-071-45/+86
| | | | | | | | | This is a follow-up to r325169, this time for all types, not just HVX vector types. Disable this by default, since it's not always safe. llvm-svn: 326915
* [Hexagon] Add patterns for compares of i1 valuesKrzysztof Parzyszek2018-02-271-2/+4
| | | | llvm-svn: 326220
* [DAGCOmbine] Ensure that (brcond (setcc ...)) is handled in a canonical manner.Amaury Sechet2018-02-231-0/+2
| | | | | | | | | | | | | | | Summary: There are transformation that change setcc into other constructs, and transform that try to reconstruct a setcc from the brcond condition. Depending on what order these transform are done, the end result differs. Most of the time, it is preferable to get a setcc as a brcond argument (and this is why brcond try to recreate the setcc in the first place) so we ensure this is done every time by also doing it at the setcc level when the only user is a brcond. Reviewers: spatel, hfinkel, niravd, craig.topper Subscribers: nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D41235 llvm-svn: 325892
* [Hexagon] Split HVX vector pair loads/stores, expand unaligned loadsKrzysztof Parzyszek2018-02-141-27/+0
| | | | llvm-svn: 325169
* [Hexagon] Extract HVX lowering and selection into HVX-specific files, NFCKrzysztof Parzyszek2018-02-061-339/+0
| | | | llvm-svn: 324392
* [Hexagon] Split HVX operations on vector pairsKrzysztof Parzyszek2018-02-061-14/+82
| | | | | | | | Vector pairs are legal types, but not every operation can work on pairs. For those operations that are legal for single vectors, generate a concat of their results on pair halves. llvm-svn: 324350
* [Hexagon] Handle lowering of SETCC via setCondCodeActionKrzysztof Parzyszek2018-02-061-2/+41
| | | | | | | | | | It was expanded directly into instructions earlier. That was to avoid loads from a constant pool for a vector negation: "xor x, splat(i1 -1)". Implement ISD opcodes QTRUE and QFALSE to denote logical vectors of all true and all false values, and handle setcc with negations through selection patterns. llvm-svn: 324348
* [Hexagon] Implement HVX codegen for vector shiftsKrzysztof Parzyszek2018-01-311-4/+18
| | | | llvm-svn: 323914
* [Hexagon] Generate constant splats instead of loads from constant poolKrzysztof Parzyszek2018-01-261-0/+21
| | | | llvm-svn: 323568
* [Hexagon] Remove unused HexagonISD opcodes, NFCKrzysztof Parzyszek2018-01-241-13/+0
| | | | llvm-svn: 323324
* [Hexagon] Add patterns for sext_inreg of HVX vector typesKrzysztof Parzyszek2018-01-231-0/+19
| | | | llvm-svn: 323250
* [Hexagon] Implement basic vector operations on vectors vNi1Krzysztof Parzyszek2018-01-231-18/+60
| | | | | | | | | | | In addition to that, make sure that there are no boolean vector types that are associated with multiple register classes. Specifically, remove v32i1 and v64i1 from integer register classes. These types will correspond to results of vector comparisons, and as such should belong to the vector predicate class. Having them in scalar registers as well makes legalization ambiguous. llvm-svn: 323229
* [Hexagon] Implement signed and unsigned multiply-high for vectorsKrzysztof Parzyszek2018-01-151-0/+50
| | | | llvm-svn: 322499
* [Hexagon] Even simpler patterns for sign- and zero-extending HVX vectorsKrzysztof Parzyszek2018-01-051-16/+4
| | | | | | Recommit r321897 with updated testcases. llvm-svn: 321908
* Revert r321894: it requires a part of another commit that is not ready yetKrzysztof Parzyszek2018-01-051-19/+0
| | | | | | | Commit message: [Hexagon] Add patterns for sext_inreg of HVX vector types llvm-svn: 321904
* Revert r321897: affected testcases were not updatedKrzysztof Parzyszek2018-01-051-4/+16
| | | | | | | Commit message: [Hexagon] Even simpler patterns for sign- and zero-extending HVX vectors llvm-svn: 321902
* [Hexagon] Even simpler patterns for sign- and zero-extending HVX vectorsKrzysztof Parzyszek2018-01-051-16/+4
| | | | llvm-svn: 321897
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