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path: root/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
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* [DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG ↵QingShan Zhang2020-01-031-0/+7
| | | | | | | | | | | for vector type as 'expand' instead of 'legal' For now, we didn't set the default operation action for SIGN_EXTEND_INREG for vector type, which is 0 by default, that is legal. However, most target didn't have native instructions to support this opcode. It should be set as expand by default, as what we did for ANY_EXTEND_VECTOR_INREG. Differential Revision: https://reviews.llvm.org/D70000
* [Hexagon] Generate vector min/max for HVXKrzysztof Parzyszek2019-08-151-0/+24
| | | | llvm-svn: 369014
* [Hexagon] Split vector pairs for ISD::SIGN_EXTEND and ISD::ZERO_EXTENDKrzysztof Parzyszek2019-02-201-0/+2
| | | | llvm-svn: 354473
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [SelectionDAG] Remove special methods for creating *_EXTEND_VECTOR_INREG ↵Craig Topper2018-11-041-1/+2
| | | | | | | | | | nodes. Move asserts into getNode. These methods were just wrappers around getNode with additional asserts (identical and repeated 3 times). But getNode already has a switch that can be used to hold these asserts that allows them to be shared for all 3 opcodes. This also enables checking on the places that create these nodes without using the wrappers. The rest of the patch is just changing all callers to use getNode directly. llvm-svn: 346087
* [Hexagon] Use shuffles when lowering "gather" shufflevectorsKrzysztof Parzyszek2018-09-121-0/+70
| | | | | | | | Shufflevector instructions in LLVM IR that extract a subset of elements of a longer input into a shorter vector can be done using VECTOR_SHUFFLEs. This will avoid expanding them into constly extracts and inserts. llvm-svn: 342091
* [Hexagon] Split CTPOP of vector pairsKrzysztof Parzyszek2018-06-061-0/+1
| | | | llvm-svn: 334109
* [Hexagon] Avoid UB when shifting unsigned integer left by 32Krzysztof Parzyszek2018-06-011-3/+4
| | | | llvm-svn: 333771
* [Hexagon] Select HVX code for vector CTPOP, CTLZ, and CTTZKrzysztof Parzyszek2018-06-011-15/+52
| | | | llvm-svn: 333760
* [Hexagon] Mark HVX vector predicate bitwise ops as legal, add patternsKrzysztof Parzyszek2018-05-161-11/+27
| | | | llvm-svn: 332525
* [Hexagon] Improve HVX instruction selection (bitcast, vsplat)Krzysztof Parzyszek2018-04-201-3/+1
| | | | | | | | | | There was some unfortunate interaction between VSPLAT and BITCAST related to the selection of constant vectors (coming from selecting shuffles). Introduce VSPLATW that always splats a 32-bit word, and can have arbitrary result type (to avoid BITCASTs of VSPLAT). Clean up the previous selection of BITCAST/VSPLAT. llvm-svn: 330471
* [Hexagon] Use legal types when lowering CONCAT_VECTORS via BUILD_VECTORKrzysztof Parzyszek2018-04-191-0/+26
| | | | llvm-svn: 330344
* [Hexagon] Rewrite non-HVX unaligned loads as pairs of aligned onesKrzysztof Parzyszek2018-03-071-58/+2
| | | | | | | | | This is a follow-up to r325169, this time for all types, not just HVX vector types. Disable this by default, since it's not always safe. llvm-svn: 326915
* [Hexagon] Split HVX vector pair loads/stores, expand unaligned loadsKrzysztof Parzyszek2018-02-141-15/+124
| | | | llvm-svn: 325169
* [Hexagon] Extract HVX lowering and selection into HVX-specific files, NFCKrzysztof Parzyszek2018-02-061-12/+210
| | | | llvm-svn: 324392
* [Hexagon] Lower concat of more than 2 vectors into build_vectorKrzysztof Parzyszek2018-02-061-6/+15
| | | | llvm-svn: 324391
* [Hexagon] Remove leftover assertKrzysztof Parzyszek2018-02-061-3/+1
| | | | llvm-svn: 324352
* [Hexagon] Split HVX operations on vector pairsKrzysztof Parzyszek2018-02-061-26/+125
| | | | | | | | Vector pairs are legal types, but not every operation can work on pairs. For those operations that are legal for single vectors, generate a concat of their results on pair halves. llvm-svn: 324350
* [Hexagon] Add helper functions to identify single/pair vector types, NFCKrzysztof Parzyszek2018-02-061-3/+15
| | | | llvm-svn: 324349
* [Hexagon] Handle lowering of SETCC via setCondCodeActionKrzysztof Parzyszek2018-02-061-69/+29
| | | | | | | | | | It was expanded directly into instructions earlier. That was to avoid loads from a constant pool for a vector negation: "xor x, splat(i1 -1)". Implement ISD opcodes QTRUE and QFALSE to denote logical vectors of all true and all false values, and handle setcc with negations through selection patterns. llvm-svn: 324348
* [Hexagon] Use V6_vmpyih for halfword multiplicationKrzysztof Parzyszek2018-02-051-5/+6
| | | | | | | Unlike V6_vmpyhv, it produces the result in the exact form that is expected without the need for a shuffle. llvm-svn: 324241
* [Hexagon] Rename HexagonISelLowering::getNode to getInstr, NFCKrzysztof Parzyszek2018-01-311-33/+33
| | | | llvm-svn: 323916
* [Hexagon] Implement HVX codegen for vector shiftsKrzysztof Parzyszek2018-01-311-0/+6
| | | | llvm-svn: 323914
* [Hexagon] Handle SETCC on vector pairs in loweringKrzysztof Parzyszek2018-01-311-1/+13
| | | | llvm-svn: 323911
* [Hexagon] Handle BUILD_VECTOR from undef values in buildHvxVectorRegKrzysztof Parzyszek2018-01-311-1/+4
| | | | llvm-svn: 323889
* [Hexagon] Generate constant splats instead of loads from constant poolKrzysztof Parzyszek2018-01-261-17/+20
| | | | llvm-svn: 323568
* [NFC] fix trivial typos in comments and documentsHiroshi Inoue2018-01-261-1/+1
| | | | | | "in in" -> "in", "on on" -> "on" etc. llvm-svn: 323508
* Remove set but unused variable IsUndef.Eric Christopher2018-01-241-2/+1
| | | | llvm-svn: 323295
* [Hexagon] Fix unused variable warning in release buildKrzysztof Parzyszek2018-01-231-0/+1
| | | | llvm-svn: 323233
* [Hexagon] Implement basic vector operations on vectors vNi1Krzysztof Parzyszek2018-01-231-84/+520
| | | | | | | | | | | In addition to that, make sure that there are no boolean vector types that are associated with multiple register classes. Specifically, remove v32i1 and v64i1 from integer register classes. These types will correspond to results of vector comparisons, and as such should belong to the vector predicate class. Having them in scalar registers as well makes legalization ambiguous. llvm-svn: 323229
* [Hexagon] Implement signed and unsigned multiply-high for vectorsKrzysztof Parzyszek2018-01-151-3/+108
| | | | llvm-svn: 322499
* [Hexagon] Add a bitcast to required type in LowerHvxMulKrzysztof Parzyszek2018-01-051-1/+2
| | | | llvm-svn: 321893
* [Hexagon] Allow construction of HVX vector predicatesKrzysztof Parzyszek2017-12-201-26/+108
| | | | | | Handle BUILD_VECTOR of boolean values. llvm-svn: 321220
* [Hexagon] Generate HVX code for vector sign-, zero- and any-extendsKrzysztof Parzyszek2017-12-181-0/+7
| | | | | | Implement any-extend as zero-extend. llvm-svn: 321004
* [Hexagon] Generate HVX code for comparisons and selectsKrzysztof Parzyszek2017-12-141-0/+71
| | | | llvm-svn: 320744
* [Hexagon] Remove vectors of i64 from valid HVX typesKrzysztof Parzyszek2017-12-141-2/+2
| | | | | | HVX does not support operations on 64-bit integers. llvm-svn: 320722
* [Hexagon] Crash in instruction selection for insert_vector_elt for HVXKrzysztof Parzyszek2017-12-111-1/+1
| | | | | | | | A wrong type was passed to insertVector, causing an out-of-bounds value to be added an an operand to HexagonISD::INSERT. This later failed in instruction selection. llvm-svn: 320369
* [Hexagon] Generate HVX code for basic arithmetic operationsKrzysztof Parzyszek2017-12-071-1/+85
| | | | | | Handle and, or, xor, add, sub, mul for vectors of i8, i16, and i32. llvm-svn: 320063
* [Hexagon] Suppress warnings on unused variables defind for asserts.Tim Shen2017-12-061-0/+2
| | | | llvm-svn: 319940
* [Hexagon] Generate HVX code for vector construction and accessKrzysztof Parzyszek2017-12-061-0/+299
Support for: - build vector, - extract vector element, subvector, - insert vector element, subvector, - shuffle. llvm-svn: 319901
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