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* [llvm] Fix some typos. NFC.Mandeep Singh Grang2017-09-151-1/+1
| | | | | | | | | | | | Reviewers: mcrosier Reviewed By: mcrosier Subscribers: mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D37922 llvm-svn: 313388
* [Hexagon] Switch to parameterized register classes for HVXKrzysztof Parzyszek2017-09-151-1/+1
| | | | | | | This removes the duplicate HVX instruction set for the 128-byte mode. Single instruction set now works for both modes (64- and 128-byte). llvm-svn: 313362
* [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use ↵Eugene Zelenko2017-07-291-16/+25
| | | | | | warnings; other minor fixes (NFC). llvm-svn: 309469
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-171-12/+12
| | | | | | Reapply r295371 with a fix for the Windows bot failures. llvm-svn: 295504
* Revert "[Hexagon] Start using regmasks on calls"Rafael Espindola2017-02-171-11/+11
| | | | | | | | | | This reverts commit r295371. It broke windows bots: http://bb.pgr.jp/builders/ninja-clang-i686-msc19-R/builds/11402/steps/test-llvm/logs/stdio llvm-svn: 295402
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-161-11/+11
| | | | | | All the cool targets are doing it... llvm-svn: 295371
* Fix "left shift of negative value -1" introduced by r294805Vitaly Buka2017-02-111-1/+1
| | | | llvm-svn: 294843
* [Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; ↵Eugene Zelenko2016-12-161-16/+37
| | | | | | other minor fixes (NFC). llvm-svn: 289907
* Fix spelling mistakes in Hexagon target comments. NFC.Simon Pilgrim2016-11-171-1/+1
| | | | | | Identified by Pedro Giffuni in PR27636. llvm-svn: 287248
* [Hexagon] Separate Hexagon subreg indices for different register classesKrzysztof Parzyszek2016-11-091-4/+4
| | | | | | | | | | | For pairs of 32-bit registers: isub_lo, isub_hi. For pairs of vector registers: vsub_lo, vsub_hi. Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg) that returns the appropriate subreg index for RegClass. llvm-svn: 286377
* Use StringRef in Pass/PassManager APIs (NFC)Mehdi Amini2016-10-011-1/+1
| | | | llvm-svn: 283004
* Make analyzeBranch family of instruction names consistentMatt Arsenault2016-09-141-4/+4
| | | | | | | analyzeBranch was renamed to use lowercase first, rename the related set to match. llvm-svn: 281506
* This reapplies r281304. The issue was that I had missedSjoerd Meijer2016-09-141-6/+2
| | | | | | to copy the new isAdd field in the tablegen data structure. llvm-svn: 281447
* Revert of r281304 as it is causing build bot failures in hexagonSjoerd Meijer2016-09-131-2/+6
| | | | | | | hwloop regression tests. These tests pass locally; will be investigating where these differences come from. llvm-svn: 281306
* This adds a new field isAdd to MCInstrDesc. The ARM and Hexagon instructionSjoerd Meijer2016-09-131-6/+2
| | | | | | | | | | | descriptions now tag add instructions, and the Hexagon backend is using this to identify loop induction statements. Patch by Sam Parker and Sjoerd Meijer. Differential Revision: https://reviews.llvm.org/D23601 llvm-svn: 281304
* MachineLoop: add methods findLoopControlBlock and findLoopPreheaderSjoerd Meijer2016-08-151-62/+11
| | | | | | | | | | | This adds two new utility functions findLoopControlBlock and findLoopPreheader to MachineLoop and MachineLoopInfo. These functions are refactored and taken from the Hexagon target as they are target independent; thus this is intendend to be a non-functional change. Differential Revision: https://reviews.llvm.org/D22959 llvm-svn: 278661
* [Hexagon] Allow non-returning calls in hardware loopsKrzysztof Parzyszek2016-08-111-2/+2
| | | | llvm-svn: 278416
* [Hexagon] Use integer instructions for floating point immediatesKrzysztof Parzyszek2016-08-101-2/+2
| | | | | | | | | | | | Floating point instructions use general purpose registers, so the few instructions that can put floating point immediates into registers are, in fact, integer instruction. Use them explicitly instead of having pseudo-instructions specifically for dealing with floating point values. Simplify the constant loading instructions (from sdata) to have only two: one for 32-bit values and one for 64-bit values: CONST32 and CONST64. llvm-svn: 278244
* [Hexagon] Find speculative loop preheader in hardware loop generationKrzysztof Parzyszek2016-07-271-10/+57
| | | | | | | | Before adding a new preheader block, check if there is a candidate block where the loop setup could be placed speculatively. This will be off by default. llvm-svn: 276919
* Rename AnalyzeBranch* to analyzeBranch*.Jacques Pienaar2016-07-151-11/+11
| | | | | | | | | | | | Summary: NFC. Rename AnalyzeBranch/AnalyzeBranchPredicate to analyzeBranch/analyzeBranchPredicate to follow LLVM coding style and be consistent with TargetInstrInfo's analyzeCompare and analyzeSelect. Reviewers: tstellarAMD, mcrosier Subscribers: mcrosier, jholewinski, jfb, arsenm, dschuff, jyknight, dsanders, nemanjai Differential Revision: https://reviews.llvm.org/D22409 llvm-svn: 275564
* CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith2016-06-301-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is mostly a mechanical change to make TargetInstrInfo API take MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator) when the argument is expected to be a valid MachineInstr. This is a general API improvement. Although it would be possible to do this one function at a time, that would demand a quadratic amount of churn since many of these functions call each other. Instead I've done everything as a block and just updated what was necessary. This is mostly mechanical fixes: adding and removing `*` and `&` operators. The only non-mechanical change is to split ARMBaseInstrInfo::getOperandLatencyImpl out from ARMBaseInstrInfo::getOperandLatency. Previously, the latter took a `MachineInstr*` which it updated to the instruction bundle leader; now, the latter calls the former either with the same `MachineInstr&` or the bundle leader. As a side effect, this removes a bunch of MachineInstr* to MachineBasicBlock::iterator implicit conversions, a necessary step toward fixing PR26753. Note: I updated WebAssembly, Lanai, and AVR (despite being off-by-default) since it turned out to be easy. I couldn't run tests for AVR since llc doesn't link with it turned on. llvm-svn: 274189
* Add optimization bisect opt-in calls for Hexagon passesAndrew Kaylor2016-04-261-0/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D19509 llvm-svn: 267593
* Revert "CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFC"Duncan P. N. Exon Smith2016-02-221-2/+2
| | | | | | | | | | This reverts commit r261504, since it's not obvious the new name is better: http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20160222/334298.html I'll recommit if we get consensus that it's the right direction. llvm-svn: 261567
* CodeGen: MachineInstr::getIterator() => getInstrIterator(), NFCDuncan P. N. Exon Smith2016-02-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | Delete MachineInstr::getIterator(), since the term "iterator" is overloaded when talking about MachineInstr. - Downcast to ilist_node in iplist::getNextNode() and getPrevNode() so that ilist_node::getIterator() is still available. - Add it back as MachineInstr::getInstrIterator(). This matches the naming in MachineBasicBlock. - Add MachineInstr::getBundleIterator(). This is explicitly called "bundle" (not matching MachineBasicBlock) to disintinguish it clearly from ilist_node::getIterator(). - Update all calls. Some of these I switched to `auto` to remove boiler-plate, since the new name is clear about the type. There was one call I updated that looked fishy, but it wasn't clear what the right answer was. This was in X86FrameLowering::inlineStackProbe(), added in r252578 in lib/Target/X86/X86FrameLowering.cpp. I opted to leave the behaviour unchanged, but I'll reply to the original commit on the list in a moment. llvm-svn: 261504
* Hexagon: Remove implicit ilist iterator conversions, NFCDuncan P. N. Exon Smith2015-10-201-6/+4
| | | | | | | | | | | | | | | | | | | There are two things out of the ordinary in this commit. First, I made a loop obviously "infinite" in HexagonInstrInfo.cpp. After checking if an instruction was at the beginning of a basic block (in which case, `break`), the loop decremented and checked the iterator for `nullptr` as the loop condition. This has never been possible (the prev pointers are always been circular, so even with the weird ilist/iplist implementation, this isn't been possible), so I removed the condition. Second, in HexagonAsmPrinter.cpp there was another case of comparing a `MachineBasicBlock::instr_iterator` against `MachineBasicBlock::end()` (which returns `MachineBasicBlock::iterator`). While not incorrect, it's fragile. I switched this to `::instr_end()`. All that said, no functionality change intended here. llvm-svn: 250778
* Fix some comment typos.Benjamin Kramer2015-08-081-3/+3
| | | | llvm-svn: 244402
* [Hexagon] Moving pass declarations out of header and in to implementation ↵Colin LeMahieu2015-06-151-0/+1
| | | | | | files. Removing unused function getSubtargetInfo from HexagonMCCodeEmitter.cpp Removing deletion of copy construction and assignment operator since parent already deletes it. llvm-svn: 239744
* [Hexagon] Generate hardware loop for a vectorized loopBrendon Cahoon2015-05-141-7/+46
| | | | | | | | | The induction variable in the vectorized loop wasn't recognized properly, so a hardware loop wasn't generated. Differential Revision: http://reviews.llvm.org/D9722 llvm-svn: 237388
* [Hexagon] Remove dead constant assignment in hardware loop passBrendon Cahoon2015-05-141-3/+9
| | | | | | | | | | | After converting a loop to a hardware loop, the pass should remove any unnecessary instructions from the old compare-and-branch code. This patch removes a dead constant assignment that was used in the compare instruction. Differential Revision: http://reviews.llvm.org/D9720 llvm-svn: 237373
* [Hexagon] Check for underflow/wrap in hardware loop passBrendon Cahoon2015-05-141-55/+307
| | | | | | | | If the loop trip count may underflow or wrap, the compiler should not generate a hardware loop since the trip count will be incorrect. llvm-svn: 237365
* [Hexagon] Generate loop1 instruction for nested loopsBrendon Cahoon2015-05-131-56/+83
| | | | | | | | loop1 is for the outer loop and loop0 is for the inner loop. Differential Revision: http://reviews.llvm.org/D9680 llvm-svn: 237266
* [Hexagon] Generate hardware loop when loop has a critical edgeBrendon Cahoon2015-05-131-13/+37
| | | | | | | | | The hardware loop pass should try to generate a hardware loop instruction when the original loop has a critical edge. Differential Revision: http://reviews.llvm.org/D9678 llvm-svn: 237258
* [Hexagon] Generate more hardware loopsBrendon Cahoon2015-05-081-133/+206
| | | | | | | | | Refactored parts of the hardware loop pass to generate more. Also, added more tests. Differential Revision: http://reviews.llvm.org/D9568 llvm-svn: 236896
* [Hexagon] Update AnalyzeBranch, etc target hooksBrendon Cahoon2015-05-081-6/+8
| | | | | | | | | | | | | Improved the AnalyzeBranch, InsertBranch, and RemoveBranch functions in order to handle more of our branch instructions. This requires changes to analyzeCompare and PredicateInstructions. Specifically, we've added support for new value compare jumps, improved handling of endloop, added more compare instructions, and improved support for predicate instructions. Differential Revision: http://reviews.llvm.org/D9559 llvm-svn: 236876
* Remove the remaining uses of abs64 and nuke it.Benjamin Kramer2015-03-091-1/+1
| | | | | | std::abs works just fine and we're already using it in many places. NFC intended. llvm-svn: 231696
* [Hexagon] Renaming A2_subri, A2_andir, A2_orir. Fixing formatting.Colin LeMahieu2015-02-051-1/+1
| | | | llvm-svn: 228326
* [Hexagon] Renaming A2_addi and formatting.Colin LeMahieu2015-02-051-4/+4
| | | | llvm-svn: 228318
* Remove unused class variables and update calls to get the subtargetEric Christopher2015-02-021-11/+3
| | | | | | off of the machine function. llvm-svn: 227837
* [Hexagon] Removing old versions of cmph and updating references.Colin LeMahieu2015-01-141-1/+1
| | | | llvm-svn: 226013
* [Hexagon] Deleting versions of compare-not that don't have encoding ↵Colin LeMahieu2015-01-141-2/+2
| | | | | | information. Updating references. llvm-svn: 226003
* [Hexagon] Removing old variants of instructions and updating references.Colin LeMahieu2014-12-191-1/+1
| | | | llvm-svn: 224612
* [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.Colin LeMahieu2014-12-191-6/+6
| | | | llvm-svn: 224556
* Reverting 224550, was not ready for commit.Colin LeMahieu2014-12-181-6/+6
| | | | llvm-svn: 224552
* [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.Colin LeMahieu2014-12-181-6/+6
| | | | llvm-svn: 224550
* [Hexagon] Updating doubleword shift usages to new versions.Colin LeMahieu2014-12-161-1/+1
| | | | llvm-svn: 224391
* [Hexagon] Adding encodings for JR class instructions. Updating complier usages.Colin LeMahieu2014-12-101-2/+2
| | | | llvm-svn: 223967
* [Hexagon] Updating rr/ri 32/64 transfer encodings and adding tests.Colin LeMahieu2014-12-091-4/+4
| | | | llvm-svn: 223821
* [Hexagon] Adding cmp* immediate form instructions.Colin LeMahieu2014-11-261-3/+3
| | | | llvm-svn: 222849
* [Hexagon] Replacing cmp* instructions with ones that contain encoding bits.Colin LeMahieu2014-11-251-3/+3
| | | | llvm-svn: 222771
* [Hexagon] Removing SUB_rr and replacing with A2_sub.Colin LeMahieu2014-11-211-1/+1
| | | | llvm-svn: 222571
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