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author | Duncan P. N. Exon Smith <dexonsmith@apple.com> | 2016-06-30 00:01:54 +0000 |
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committer | Duncan P. N. Exon Smith <dexonsmith@apple.com> | 2016-06-30 00:01:54 +0000 |
commit | 9cfc75c214d42eebd74f9f5f5d20d453404d5db4 (patch) | |
tree | 0f9f9110f564b6287a4db4cdf9e6097d19085c7e /llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp | |
parent | c3701e8b9252498e2ed27a99238f71cb07dd43a4 (diff) | |
download | bcm5719-llvm-9cfc75c214d42eebd74f9f5f5d20d453404d5db4.tar.gz bcm5719-llvm-9cfc75c214d42eebd74f9f5f5d20d453404d5db4.zip |
CodeGen: Use MachineInstr& in TargetInstrInfo, NFC
This is mostly a mechanical change to make TargetInstrInfo API take
MachineInstr& (instead of MachineInstr* or MachineBasicBlock::iterator)
when the argument is expected to be a valid MachineInstr. This is a
general API improvement.
Although it would be possible to do this one function at a time, that
would demand a quadratic amount of churn since many of these functions
call each other. Instead I've done everything as a block and just
updated what was necessary.
This is mostly mechanical fixes: adding and removing `*` and `&`
operators. The only non-mechanical change is to split
ARMBaseInstrInfo::getOperandLatencyImpl out from
ARMBaseInstrInfo::getOperandLatency. Previously, the latter took a
`MachineInstr*` which it updated to the instruction bundle leader; now,
the latter calls the former either with the same `MachineInstr&` or the
bundle leader.
As a side effect, this removes a bunch of MachineInstr* to
MachineBasicBlock::iterator implicit conversions, a necessary step
toward fixing PR26753.
Note: I updated WebAssembly, Lanai, and AVR (despite being
off-by-default) since it turned out to be easy. I couldn't run tests
for AVR since llc doesn't link with it turned on.
llvm-svn: 274189
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp')
-rw-r--r-- | llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp index f5a648a8f58..8548d612129 100644 --- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -450,8 +450,8 @@ bool HexagonHardwareLoops::findInductionRegister(MachineLoop *L, unsigned CmpReg1 = 0, CmpReg2 = 0; int CmpImm = 0, CmpMask = 0; - bool CmpAnalyzed = TII->analyzeCompare(PredI, CmpReg1, CmpReg2, - CmpMask, CmpImm); + bool CmpAnalyzed = + TII->analyzeCompare(*PredI, CmpReg1, CmpReg2, CmpMask, CmpImm); // Fail if the compare was not analyzed, or it's not comparing a register // with an immediate value. Not checking the mask here, since we handle // the individual compare opcodes (including A4_cmpb*) later on. @@ -620,8 +620,8 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L, unsigned CmpReg1 = 0, CmpReg2 = 0; int Mask = 0, ImmValue = 0; - bool AnalyzedCmp = TII->analyzeCompare(CondI, CmpReg1, CmpReg2, - Mask, ImmValue); + bool AnalyzedCmp = + TII->analyzeCompare(*CondI, CmpReg1, CmpReg2, Mask, ImmValue); if (!AnalyzedCmp) return nullptr; @@ -1420,7 +1420,7 @@ bool HexagonHardwareLoops::loopCountMayWrapOrUnderFlow( unsigned CmpReg1 = 0, CmpReg2 = 0; int CmpMask = 0, CmpValue = 0; - if (!TII->analyzeCompare(MI, CmpReg1, CmpReg2, CmpMask, CmpValue)) + if (!TII->analyzeCompare(*MI, CmpReg1, CmpReg2, CmpMask, CmpValue)) continue; MachineBasicBlock *TBB = 0, *FBB = 0; |