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authorColin LeMahieu <colinl@codeaurora.org>2014-12-18 23:27:51 +0000
committerColin LeMahieu <colinl@codeaurora.org>2014-12-18 23:27:51 +0000
commit9000481cda759f40ef471ef4bb91079374daa0ed (patch)
tree7c8269059688681bab4c3f5339fda4760eb18210 /llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
parent0fc95ad7584eacbf5b82a4890709e54b44318351 (diff)
downloadbcm5719-llvm-9000481cda759f40ef471ef4bb91079374daa0ed.tar.gz
bcm5719-llvm-9000481cda759f40ef471ef4bb91079374daa0ed.zip
[Hexagon] Adding loop0/1 sp0/1/2loop0 instructions.
llvm-svn: 224550
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp')
-rw-r--r--llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp12
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
index 39ed1abb5b8..cbb80f307d2 100644
--- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -285,8 +285,8 @@ INITIALIZE_PASS_END(HexagonHardwareLoops, "hwloops",
/// \brief Returns true if the instruction is a hardware loop instruction.
static bool isHardwareLoop(const MachineInstr *MI) {
- return MI->getOpcode() == Hexagon::LOOP0_r ||
- MI->getOpcode() == Hexagon::LOOP0_i;
+ return MI->getOpcode() == Hexagon::J2_loop0r ||
+ MI->getOpcode() == Hexagon::J2_loop0i;
}
FunctionPass *llvm::createHexagonHardwareLoops() {
@@ -1086,7 +1086,7 @@ bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L) {
BuildMI(*Preheader, InsertPos, DL, TII->get(TargetOpcode::COPY), CountReg)
.addReg(TripCount->getReg(), 0, TripCount->getSubReg());
// Add the Loop instruction to the beginning of the loop.
- BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::LOOP0_r))
+ BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::J2_loop0r))
.addMBB(LoopStart)
.addReg(CountReg);
} else {
@@ -1095,14 +1095,14 @@ bool HexagonHardwareLoops::convertToHardwareLoop(MachineLoop *L) {
// if the immediate fits in the instructions. Otherwise, we need to
// create a new virtual register.
int64_t CountImm = TripCount->getImm();
- if (!TII->isValidOffset(Hexagon::LOOP0_i, CountImm)) {
+ if (!TII->isValidOffset(Hexagon::J2_loop0i, CountImm)) {
unsigned CountReg = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass);
BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::A2_tfrsi), CountReg)
.addImm(CountImm);
- BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::LOOP0_r))
+ BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::J2_loop0r))
.addMBB(LoopStart).addReg(CountReg);
} else
- BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::LOOP0_i))
+ BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::J2_loop0i))
.addMBB(LoopStart).addImm(CountImm);
}
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