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author | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2016-09-13 08:51:59 +0000 |
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committer | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2016-09-13 08:51:59 +0000 |
commit | 520a18df9ca30e4cacdb4cbfa79fa18b70b724db (patch) | |
tree | 08baff5221af2e2425af58aa16a3b44d1574d8d2 /llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp | |
parent | a82c4b5df847c6153bfc09c08a39cc0c919175ef (diff) | |
download | bcm5719-llvm-520a18df9ca30e4cacdb4cbfa79fa18b70b724db.tar.gz bcm5719-llvm-520a18df9ca30e4cacdb4cbfa79fa18b70b724db.zip |
Revert of r281304 as it is causing build bot failures in hexagon
hwloop regression tests. These tests pass locally; will be investigating
where these differences come from.
llvm-svn: 281306
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp')
-rw-r--r-- | llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp index 45e61485410..930747faa0d 100644 --- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -411,8 +411,10 @@ bool HexagonHardwareLoops::findInductionRegister(MachineLoop *L, unsigned PhiOpReg = Phi->getOperand(i).getReg(); MachineInstr *DI = MRI->getVRegDef(PhiOpReg); + unsigned UpdOpc = DI->getOpcode(); + bool isAdd = (UpdOpc == Hexagon::A2_addi || UpdOpc == Hexagon::A2_addp); - if (DI->getDesc().isAdd()) { + if (isAdd) { // If the register operand to the add is the PHI we're looking at, this // meets the induction pattern. unsigned IndReg = DI->getOperand(1).getReg(); @@ -1590,8 +1592,10 @@ bool HexagonHardwareLoops::fixupInductionVariable(MachineLoop *L) { unsigned PhiReg = Phi->getOperand(i).getReg(); MachineInstr *DI = MRI->getVRegDef(PhiReg); + unsigned UpdOpc = DI->getOpcode(); + bool isAdd = (UpdOpc == Hexagon::A2_addi || UpdOpc == Hexagon::A2_addp); - if (DI->getDesc().isAdd()) { + if (isAdd) { // If the register operand to the add/sub is the PHI we are looking // at, this meets the induction pattern. unsigned IndReg = DI->getOperand(1).getReg(); |