summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
Commit message (Expand)AuthorAgeFilesLines
* Sink all InitializePasses.h includesReid Kleckner2019-11-131-0/+1
* Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-151-19/+19
* Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders2019-08-011-18/+15
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [Hexagon] Check validity of register class when generating bitsplitKrzysztof Parzyszek2018-08-301-0/+4
* [Hexagon] Silence -Wuninitialized warning from GCC 5.4, NFCKrzysztof Parzyszek2018-08-131-0/+4
* [Hexagon] Simplify A4_rcmp[n]eqi R, 0Krzysztof Parzyszek2018-07-301-0/+123
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-6/+7
* [Hexagon] Fix alignment calculation of stack objects in Hexagon bit trackerKrzysztof Parzyszek2018-02-201-5/+3
* [NFC] fix trivial typos in comments and documentsHiroshi Inoue2018-01-261-1/+1
* MachineFunction: Return reference from getFunction(); NFCMatthias Braun2017-12-151-2/+2
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-1/+1
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-301-11/+11
* [CodeGen] Rename functions PrintReg* to printReg*Francis Visoiu Mistrih2017-11-281-7/+7
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
* Set hasSideEffects=0 for PHI and fix affected passesAlex Bradbury2017-11-081-3/+2
* [Hexagon] Make getHexagonSubRegIndex take reference instead of pointerKrzysztof Parzyszek2017-09-251-7/+7
* [Hexagon] Switch to parameterized register classes for HVXKrzysztof Parzyszek2017-09-151-12/+5
* [Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use wa...Eugene Zelenko2017-07-261-17/+23
* [NFC] Move DEBUG_TYPE below includes in HexagonJakub Kuderski2017-07-131-2/+2
* [Hexagon] Fix some more -Wimplicit-fallthrough warnings. NFCI.Simon Pilgrim2017-07-071-0/+2
* Sort the remaining #include lines in include/... and lib/....Chandler Carruth2017-06-061-1/+1
* [Hexagon] Only increment debug counters if debug option is presentKrzysztof Parzyszek2017-04-251-6/+11
* Move size and alignment information of regclass to TargetRegisterInfoKrzysztof Parzyszek2017-04-241-6/+7
* [Hexagon] Fixes to the bitsplit generationKrzysztof Parzyszek2017-03-091-11/+46
* [Hexagon] Use correct offset when extracting from the high wordKrzysztof Parzyszek2017-03-081-0/+1
* [Hexagon] Check for presence before looking registers up in bit trackerKrzysztof Parzyszek2017-03-071-0/+4
* [Hexagon] Generate bitsplit instructionKrzysztof Parzyszek2017-03-071-1/+118
* [Hexagon] Do not insert instructions before PHI nodesKrzysztof Parzyszek2017-03-071-1/+3
* [Hexagon] Generate extract instructions more aggressivelyKrzysztof Parzyszek2017-02-281-1/+201
* Drop graph_ prefixDaniel Berlin2017-02-091-2/+2
* GraphTraits: Add range versions of graph traits functions (graph_nodes, graph...Daniel Berlin2017-02-091-9/+6
* "Use" lambda captures which are otherwise only used in asserts. NFCDavid L. Jones2017-01-131-0/+1
* [CodeGen] Rename MachineInstrBuilder::addOperand. NFCDiana Picus2017-01-131-1/+1
* [Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; ot...Eugene Zelenko2016-12-131-102/+87
* [Hexagon] Separate Hexagon subreg indices for different register classesKrzysztof Parzyszek2016-11-091-44/+58
* [Hexagon] Avoid replacing full regs with subregisters in tied operandsKrzysztof Parzyszek2016-10-061-0/+20
* Use StringRef in Pass/PassManager APIs (NFC)Mehdi Amini2016-10-011-1/+1
* [Hexagon] Standardize next batch of pseudo instructionsKrzysztof Parzyszek2016-08-161-5/+5
* Use the range variant of find_if instead of unpacking begin/endDavid Majnemer2016-08-121-2/+2
* Use the range variant of find instead of unpacking begin/endDavid Majnemer2016-08-111-1/+1
* [Hexagon] Use integer instructions for floating point immediatesKrzysztof Parzyszek2016-08-101-3/+3
* [Hexagon] Validate register class when doing bit simplificationKrzysztof Parzyszek2016-08-041-10/+33
* [Hexagon] Generate COPY/REG_SEQUENCE more aggressively for vectorsKrzysztof Parzyszek2016-08-031-21/+27
* [Hexagon] Recognize vcombine in copy propagationKrzysztof Parzyszek2016-08-021-2/+8
* [HexagonBitSimplify] Remove dead code.Davide Italiano2016-07-301-18/+0
* [Hexagon] Gracefully handle reg class mismatch in HexagonLoopRescheduleKrzysztof Parzyszek2016-07-261-13/+19
* [Hexagon] Rerun bit tracker on new instructions in RIEKrzysztof Parzyszek2016-07-261-5/+7
* [Hexagon] Bitwise operations for insert/extract word not simplifiedKrzysztof Parzyszek2016-07-261-19/+70
* Hexagon: Avoid implicit iterator conversions, NFCDuncan P. N. Exon Smith2016-07-121-5/+4
OpenPOWER on IntegriCloud