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author | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-28 12:42:37 +0000 |
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committer | Francis Visoiu Mistrih <francisvm@yahoo.com> | 2017-11-28 12:42:37 +0000 |
commit | 9d419d3b0cfda0f85d88633bd8620cd65ccb0498 (patch) | |
tree | e1fa028a9c3a8d514e67b9bac321519331979dea /llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp | |
parent | 8dc603b03147c91ff4e66b8bfc934aad6c4cb4b3 (diff) | |
download | bcm5719-llvm-9d419d3b0cfda0f85d88633bd8620cd65ccb0498.tar.gz bcm5719-llvm-9d419d3b0cfda0f85d88633bd8620cd65ccb0498.zip |
[CodeGen] Rename functions PrintReg* to printReg*
LLVM Coding Standards:
Function names should be verb phrases (as they represent actions), and
command-like function should be imperative. The name should be camel
case, and start with a lower case letter (e.g. openFile() or isFoo()).
Differential Revision: https://reviews.llvm.org/D40416
llvm-svn: 319168
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp')
-rw-r--r-- | llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp index a1f9e813cb2..cbf1b0dc040 100644 --- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -173,7 +173,7 @@ namespace { raw_ostream &operator<< (raw_ostream &OS, const PrintRegSet &P) { OS << '{'; for (unsigned R = P.RS.find_first(); R; R = P.RS.find_next(R)) - OS << ' ' << PrintReg(R, P.TRI); + OS << ' ' << printReg(R, P.TRI); OS << " }"; return OS; } @@ -2453,7 +2453,7 @@ bool BitSimplification::simplifyExtractLow(MachineInstr *MI, return false; DEBUG({ - dbgs() << __func__ << " on reg: " << PrintReg(RD.Reg, &HRI, RD.Sub) + dbgs() << __func__ << " on reg: " << printReg(RD.Reg, &HRI, RD.Sub) << ", MI: " << *MI; dbgs() << "Cell: " << RC << '\n'; dbgs() << "Expected bitfield size: " << Len << " bits, " @@ -3004,9 +3004,9 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) { DEBUG({ dbgs() << "Phis: {"; for (auto &I : Phis) { - dbgs() << ' ' << PrintReg(I.DefR, HRI) << "=phi(" - << PrintReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber() - << ',' << PrintReg(I.LR.Reg, HRI, I.LR.Sub) << ":b" + dbgs() << ' ' << printReg(I.DefR, HRI) << "=phi(" + << printReg(I.PR.Reg, HRI, I.PR.Sub) << ":b" << I.PB->getNumber() + << ',' << printReg(I.LR.Reg, HRI, I.LR.Sub) << ":b" << I.LB->getNumber() << ')'; } dbgs() << " }\n"; @@ -3126,8 +3126,8 @@ bool HexagonLoopRescheduling::processLoop(LoopCand &C) { for (unsigned i = 0, n = Groups.size(); i < n; ++i) { InstrGroup &G = Groups[i]; dbgs() << "Group[" << i << "] inp: " - << PrintReg(G.Inp.Reg, HRI, G.Inp.Sub) - << " out: " << PrintReg(G.Out.Reg, HRI, G.Out.Sub) << "\n"; + << printReg(G.Inp.Reg, HRI, G.Inp.Sub) + << " out: " << printReg(G.Out.Reg, HRI, G.Out.Sub) << "\n"; for (unsigned j = 0, m = G.Ins.size(); j < m; ++j) dbgs() << " " << *G.Ins[j]; } |