diff options
author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-08-10 16:46:36 +0000 |
---|---|---|
committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-08-10 16:46:36 +0000 |
commit | a3386501afd12a5680545c9c462fac67561a48fa (patch) | |
tree | f93b1e2df00cf61ee5c224d03ac3ff7fc5361b6b /llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp | |
parent | b2a9c0252179d9334967266182bad77c1d3e6579 (diff) | |
download | bcm5719-llvm-a3386501afd12a5680545c9c462fac67561a48fa.tar.gz bcm5719-llvm-a3386501afd12a5680545c9c462fac67561a48fa.zip |
[Hexagon] Use integer instructions for floating point immediates
Floating point instructions use general purpose registers, so the few
instructions that can put floating point immediates into registers are,
in fact, integer instruction. Use them explicitly instead of having
pseudo-instructions specifically for dealing with floating point values.
Simplify the constant loading instructions (from sdata) to have only two:
one for 32-bit values and one for 64-bit values: CONST32 and CONST64.
llvm-svn: 278244
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp')
-rw-r--r-- | llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp index d1c75b3add9..6de62f13c65 100644 --- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp @@ -1353,8 +1353,8 @@ bool ConstGeneration::isTfrConst(const MachineInstr &MI) { case Hexagon::A2_tfrpi: case Hexagon::TFR_PdTrue: case Hexagon::TFR_PdFalse: - case Hexagon::CONST32_Int_Real: - case Hexagon::CONST64_Int_Real: + case Hexagon::CONST32: + case Hexagon::CONST64: return true; } return false; @@ -1389,7 +1389,7 @@ unsigned ConstGeneration::genTfrConst(const TargetRegisterClass *RC, int64_t C, return Reg; } - BuildMI(B, At, DL, HII.get(Hexagon::CONST64_Int_Real), Reg) + BuildMI(B, At, DL, HII.get(Hexagon::CONST64), Reg) .addImm(C); return Reg; } |