diff options
| author | Alex Richardson <Alexander.Richardson@cl.cam.ac.uk> | 2019-12-13 11:28:20 +0000 |
|---|---|---|
| committer | Alex Richardson <Alexander.Richardson@cl.cam.ac.uk> | 2019-12-13 12:22:03 +0000 |
| commit | be15dfa88fb1ed94d12f374797f98ede6808f809 (patch) | |
| tree | 46d331f25e9e482fa8d4d422edd8916346e983b9 /llvm/lib/Target/ARM | |
| parent | 2bbd32f5e8f0f62d895966e2623d9bdb9778b50b (diff) | |
| download | bcm5719-llvm-be15dfa88fb1ed94d12f374797f98ede6808f809.tar.gz bcm5719-llvm-be15dfa88fb1ed94d12f374797f98ede6808f809.zip | |
[NFC] Use EVT instead of bool for getSetCCInverse()
Summary:
The use of a boolean isInteger flag (generally initialized using
VT.isInteger()) caused errors in our out-of-tree CHERI backend
(https://github.com/CTSRD-CHERI/llvm-project).
In our backend, pointers use a separate ValueType (iFATPTR) and therefore
.isInteger() returns false. This meant that getSetCCInverse() was using the
floating-point variant and generated incorrect code for us:
`(void *)0x12033091e < (void *)0xffffffffffffffff` would return false.
Committing this change will significantly reduce our merge conflicts
for each upstream merge.
Reviewers: spatel, bogner
Reviewed By: bogner
Subscribers: wuzish, arsenm, sdardis, nemanjai, jvesely, nhaehnle, hiraditya, kbarton, jrtc27, atanasyan, jsji, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70917
Diffstat (limited to 'llvm/lib/Target/ARM')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMISelLowering.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index e38ce70a8dc..015144079de 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -4952,7 +4952,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { Opcode = ARMISD::CSINC; std::swap(TrueVal, FalseVal); std::swap(TVal, FVal); - CC = ISD::getSetCCInverse(CC, true); + CC = ISD::getSetCCInverse(CC, LHS.getValueType()); } if (Opcode) { @@ -4962,7 +4962,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { HasLowerConstantMaterializationCost(FVal, TVal, Subtarget)) { std::swap(TrueVal, FalseVal); std::swap(TVal, FVal); - CC = ISD::getSetCCInverse(CC, true); + CC = ISD::getSetCCInverse(CC, LHS.getValueType()); } // Attempt to use ZR checking TVal is 0, possibly inverting the condition @@ -4971,7 +4971,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { if (FVal == 0 && Opcode != ARMISD::CSINC) { std::swap(TrueVal, FalseVal); std::swap(TVal, FVal); - CC = ISD::getSetCCInverse(CC, true); + CC = ISD::getSetCCInverse(CC, LHS.getValueType()); } if (TVal == 0) TrueVal = DAG.getRegister(ARM::ZR, MVT::i32); @@ -5015,7 +5015,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { ARMCC::CondCodes CondCode = IntCCToARMCC(CC); if (CondCode == ARMCC::LT || CondCode == ARMCC::LE || CondCode == ARMCC::VC || CondCode == ARMCC::NE) { - CC = ISD::getSetCCInverse(CC, true); + CC = ISD::getSetCCInverse(CC, LHS.getValueType()); std::swap(TrueVal, FalseVal); } } @@ -14226,7 +14226,7 @@ static SDValue PerformHWLoopCombine(SDNode *N, return SDValue(); if (Negate) - CC = ISD::getSetCCInverse(CC, true); + CC = ISD::getSetCCInverse(CC, /* Integer inverse */ MVT::i32); auto IsTrueIfZero = [](ISD::CondCode CC, int Imm) { return (CC == ISD::SETEQ && Imm == 0) || |

