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* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-2491-62117/+0
* AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.Tim Northover2014-05-247-0/+53
* ARM64: extract a 32-bit subreg when selecting an inreg extendTim Northover2014-05-241-10/+19
* [ARM64] Fix a bug in shuffle vector lowering to generate corect vext ISD with...Jiangning Liu2014-05-231-15/+14
* ARM64: remove '#' from annotation of add/sub immediateTim Northover2014-05-221-1/+1
* ARM64: these work tooTim Northover2014-05-221-2/+0
* Yes they doTim Northover2014-05-221-1/+0
* ARM64: model pre/post-indexed operations properly.Tim Northover2014-05-229-336/+241
* ARM64: separate load/store operands to simplify assemblerTim Northover2014-05-2211-2570/+2456
* ARM64: assert if we see i64 -> i64 extend in the DAG.Tim Northover2014-05-221-4/+2
* Fix typo.Eric Christopher2014-05-221-1/+1
* Reset the subtarget for DAGToDAG on every iteration of runOnMachineFunction.Eric Christopher2014-05-221-1/+2
* Sort includes.Eric Christopher2014-05-221-1/+1
* Fix compilation issues.Eric Christopher2014-05-211-1/+1
* Make early if conversion dependent upon the subtarget and addEric Christopher2014-05-213-6/+11
* [ARM64] PR19792: Fix cycle in DAG after performPostLD1CombineAdam Nemet2014-05-201-1/+6
* TableGen: convert InstAlias's Emit bit to an int.Tim Northover2014-05-202-68/+65
* [ARM64] Adds Cortex-A53 scheduling support for vector load/store post.Chad Rosier2014-05-194-60/+152
* [ARM64] Split tbz/tbnz into W/X register variantBradley Smith2014-05-198-64/+144
* Resolving MSVC warnings about switch statements with a default label, but no ...Aaron Ballman2014-05-191-7/+4
* SDAG: Legalize vector BSWAP into a shuffle if the shuffle is legal but the bs...Benjamin Kramer2014-05-191-0/+2
* Target: remove old constructors for CallLoweringInfoSaleem Abdulrasool2014-05-172-9/+9
* Target: change member from reference to pointerSaleem Abdulrasool2014-05-171-1/+1
* Delete getAliasedGlobal.Rafael Espindola2014-05-161-1/+1
* [ARM64] Increases the Sched Model accuracy for Cortex-A53.Chad Rosier2014-05-166-51/+228
* [ARM64] Fix wrong comment in load/store optimization pass.Tilmann Scheller2014-05-161-1/+1
* Revert "Implement global merge optimization for global variables."Rafael Espindola2014-05-162-18/+0
* TableGen: fix operand counting for aliasesTim Northover2014-05-162-70/+5
* ARM64: disable printing of "fcmXY ..., #0" aliasesTim Northover2014-05-161-2/+2
* ARM64: disable printing of swapped compare-mask aliasesTim Northover2014-05-161-12/+12
* ARM64: disable printing of LDUR -> LDR aliasesTim Northover2014-05-161-24/+40
* ARM64: give TST aliases priority over ANDS.Tim Northover2014-05-161-10/+10
* ARM64: give MOV priority over shorter ORR when printing aliases.Tim Northover2014-05-161-11/+17
* ARM64: give NEG priority over SUB when printing aliases.Tim Northover2014-05-162-23/+21
* ARM64: disable printing of "lslv" type aliasesTim Northover2014-05-161-1/+1
* [ARM64]Implement NEON post-increment LD1(lane) and post-increment LD1R.Hao Liu2014-05-163-12/+148
* Implement global merge optimization for global variables.Jiangning Liu2014-05-152-0/+18
* [ARM64] Improve diagnostics for Cn operands in SYS instructionsBradley Smith2014-05-151-69/+24
* TableGen: use correct MIOperand when printing aliasesTim Northover2014-05-151-16/+0
* ARM64: print correct aliases for NEON mov & mvn instructionsTim Northover2014-05-152-15/+7
* TableGen/ARM64: print aliases even if they have syntax variants.Tim Northover2014-05-151-12/+9
* ARM64: add correct vector registers during asm parsingTim Northover2014-05-152-5/+23
* [ARM64] Improve load/store diagnostics and forbid 32-bit register addressesBradley Smith2014-05-151-2/+11
* [ARM64] Parse fixed vector lanes properly so that diagnostics can be emittedBradley Smith2014-05-153-81/+92
* [ARM64] Add/Fixup diagnostics for floating point immediatesBradley Smith2014-05-152-3/+18
* [ARM64] Add condition code operand type such that proper diagnostics can be e...Bradley Smith2014-05-154-32/+62
* [ARM64] Add more simple diagnostics for immediate/shift rangesBradley Smith2014-05-152-10/+25
* Fix typosAlp Toker2014-05-151-2/+2
* [ARM64] Support aggressive fastcc/tailcallopt breaking ABI by popping out arg...Jiangning Liu2014-05-155-101/+377
* Rename ComputeMaskedBits to computeKnownBits. "Masked" has beenJay Foad2014-05-143-11/+11
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