AArch64/ARM64: remove AArch64 from tree prior to renaming ARM64.

I'm doing this in two phases for a better "git blame" record. This
commit removes the previous AArch64 backend and redirects all
functionality to ARM64. It also deduplicates test-lines and removes
orphaned AArch64 tests.

The next step will be "git mv ARM64 AArch64" and rewire most of the
tests.

Hopefully LLVM is still functional, though it would be even better if
no-one ever had to care because the rename happens straight
afterwards.

llvm-svn: 209576

7 files changed, 53 insertions, 0 deletions

diff --git a/llvm/lib/Target/ARM64/ARM64AsmPrinter.cpp b/llvm/lib/Target/ARM64/ARM64AsmPrinter.cpp
index 78f9ed12f56..7e17985bf4a 100644
--- a/llvm/lib/Target/ARM64/ARM64AsmPrinter.cpp
+++ b/llvm/lib/Target/ARM64/ARM64AsmPrinter.cpp
@@ -508,4 +508,7 @@ void ARM64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
 extern "C" void LLVMInitializeARM64AsmPrinter() {
   RegisterAsmPrinter<ARM64AsmPrinter> X(TheARM64leTarget);
   RegisterAsmPrinter<ARM64AsmPrinter> Y(TheARM64beTarget);
+
+  RegisterAsmPrinter<ARM64AsmPrinter> Z(TheAArch64leTarget);
+  RegisterAsmPrinter<ARM64AsmPrinter> W(TheAArch64beTarget);
 }
diff --git a/llvm/lib/Target/ARM64/ARM64TargetMachine.cpp b/llvm/lib/Target/ARM64/ARM64TargetMachine.cpp
index 5a8c5c6015d..fc73145be3f 100644
--- a/llvm/lib/Target/ARM64/ARM64TargetMachine.cpp
+++ b/llvm/lib/Target/ARM64/ARM64TargetMachine.cpp
@@ -57,6 +57,9 @@ extern "C" void LLVMInitializeARM64Target() {
   // Register the target.
   RegisterTargetMachine<ARM64leTargetMachine> X(TheARM64leTarget);
   RegisterTargetMachine<ARM64beTargetMachine> Y(TheARM64beTarget);
+
+  RegisterTargetMachine<ARM64leTargetMachine> Z(TheAArch64leTarget);
+  RegisterTargetMachine<ARM64beTargetMachine> W(TheAArch64beTarget);
 }
 
 /// TargetMachine ctor - Create an ARM64 architecture model.
diff --git a/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp b/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
index 0c422c5cece..4d710db1d93 100644
--- a/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
+++ b/llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
@@ -3957,6 +3957,9 @@ ARM64AsmParser::classifySymbolRef(const MCExpr *Expr,
 extern "C" void LLVMInitializeARM64AsmParser() {
   RegisterMCAsmParser<ARM64AsmParser> X(TheARM64leTarget);
   RegisterMCAsmParser<ARM64AsmParser> Y(TheARM64beTarget);
+
+  RegisterMCAsmParser<ARM64AsmParser> Z(TheAArch64leTarget);
+  RegisterMCAsmParser<ARM64AsmParser> W(TheAArch64beTarget);
 }
 
 #define GET_REGISTER_MATCHER
diff --git a/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp b/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
index 4fa9339d2b7..bb47b3a0982 100644
--- a/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
+++ b/llvm/lib/Target/ARM64/Disassembler/ARM64Disassembler.cpp
@@ -242,6 +242,15 @@ extern "C" void LLVMInitializeARM64Disassembler() {
                                        createARM64ExternalSymbolizer);
   TargetRegistry::RegisterMCSymbolizer(TheARM64beTarget,
                                        createARM64ExternalSymbolizer);
+
+  TargetRegistry::RegisterMCDisassembler(TheAArch64leTarget,
+                                         createARM64Disassembler);
+  TargetRegistry::RegisterMCDisassembler(TheAArch64beTarget,
+                                         createARM64Disassembler);
+  TargetRegistry::RegisterMCSymbolizer(TheAArch64leTarget,
+                                       createARM64ExternalSymbolizer);
+  TargetRegistry::RegisterMCSymbolizer(TheAArch64beTarget,
+                                       createARM64ExternalSymbolizer);
 }
 
 static const unsigned FPR128DecoderTable[] = {
diff --git a/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.cpp b/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.cpp
index 9775a471f52..079d3588f6e 100644
--- a/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.cpp
+++ b/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.cpp
@@ -141,44 +141,70 @@ extern "C" void LLVMInitializeARM64TargetMC() {
   // Register the MC asm info.
   RegisterMCAsmInfoFn X(TheARM64leTarget, createARM64MCAsmInfo);
   RegisterMCAsmInfoFn Y(TheARM64beTarget, createARM64MCAsmInfo);
+  RegisterMCAsmInfoFn Z(TheAArch64leTarget, createARM64MCAsmInfo);
+  RegisterMCAsmInfoFn W(TheAArch64beTarget, createARM64MCAsmInfo);
 
   // Register the MC codegen info.
   TargetRegistry::RegisterMCCodeGenInfo(TheARM64leTarget,
                                         createARM64MCCodeGenInfo);
   TargetRegistry::RegisterMCCodeGenInfo(TheARM64beTarget,
                                         createARM64MCCodeGenInfo);
+  TargetRegistry::RegisterMCCodeGenInfo(TheAArch64leTarget,
+                                        createARM64MCCodeGenInfo);
+  TargetRegistry::RegisterMCCodeGenInfo(TheAArch64beTarget,
+                                        createARM64MCCodeGenInfo);
 
   // Register the MC instruction info.
   TargetRegistry::RegisterMCInstrInfo(TheARM64leTarget, createARM64MCInstrInfo);
   TargetRegistry::RegisterMCInstrInfo(TheARM64beTarget, createARM64MCInstrInfo);
+  TargetRegistry::RegisterMCInstrInfo(TheAArch64leTarget, createARM64MCInstrInfo);
+  TargetRegistry::RegisterMCInstrInfo(TheAArch64beTarget, createARM64MCInstrInfo);
 
   // Register the MC register info.
   TargetRegistry::RegisterMCRegInfo(TheARM64leTarget, createARM64MCRegisterInfo);
   TargetRegistry::RegisterMCRegInfo(TheARM64beTarget, createARM64MCRegisterInfo);
+  TargetRegistry::RegisterMCRegInfo(TheAArch64leTarget, createARM64MCRegisterInfo);
+  TargetRegistry::RegisterMCRegInfo(TheAArch64beTarget, createARM64MCRegisterInfo);
 
   // Register the MC subtarget info.
   TargetRegistry::RegisterMCSubtargetInfo(TheARM64leTarget,
                                           createARM64MCSubtargetInfo);
   TargetRegistry::RegisterMCSubtargetInfo(TheARM64beTarget,
                                           createARM64MCSubtargetInfo);
+  TargetRegistry::RegisterMCSubtargetInfo(TheAArch64leTarget,
+                                          createARM64MCSubtargetInfo);
+  TargetRegistry::RegisterMCSubtargetInfo(TheAArch64beTarget,
+                                          createARM64MCSubtargetInfo);
 
   // Register the asm backend.
   TargetRegistry::RegisterMCAsmBackend(TheARM64leTarget, createARM64leAsmBackend);
   TargetRegistry::RegisterMCAsmBackend(TheARM64beTarget, createARM64beAsmBackend);
+  TargetRegistry::RegisterMCAsmBackend(TheAArch64leTarget, createARM64leAsmBackend);
+  TargetRegistry::RegisterMCAsmBackend(TheAArch64beTarget, createARM64beAsmBackend);
 
   // Register the MC Code Emitter
   TargetRegistry::RegisterMCCodeEmitter(TheARM64leTarget,
                                         createARM64MCCodeEmitter);
   TargetRegistry::RegisterMCCodeEmitter(TheARM64beTarget,
                                         createARM64MCCodeEmitter);
+  TargetRegistry::RegisterMCCodeEmitter(TheAArch64leTarget,
+                                        createARM64MCCodeEmitter);
+  TargetRegistry::RegisterMCCodeEmitter(TheAArch64beTarget,
+                                        createARM64MCCodeEmitter);
 
   // Register the object streamer.
   TargetRegistry::RegisterMCObjectStreamer(TheARM64leTarget, createMCStreamer);
   TargetRegistry::RegisterMCObjectStreamer(TheARM64beTarget, createMCStreamer);
+  TargetRegistry::RegisterMCObjectStreamer(TheAArch64leTarget, createMCStreamer);
+  TargetRegistry::RegisterMCObjectStreamer(TheAArch64beTarget, createMCStreamer);
 
   // Register the MCInstPrinter.
   TargetRegistry::RegisterMCInstPrinter(TheARM64leTarget,
                                         createARM64MCInstPrinter);
   TargetRegistry::RegisterMCInstPrinter(TheARM64beTarget,
                                         createARM64MCInstPrinter);
+  TargetRegistry::RegisterMCInstPrinter(TheAArch64leTarget,
+                                        createARM64MCInstPrinter);
+  TargetRegistry::RegisterMCInstPrinter(TheAArch64beTarget,
+                                        createARM64MCInstPrinter);
 }
diff --git a/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.h b/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.h
index 954dcdbb8bc..f2e9c17a378 100644
--- a/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.h
+++ b/llvm/lib/Target/ARM64/MCTargetDesc/ARM64MCTargetDesc.h
@@ -31,6 +31,8 @@ class raw_ostream;
 
 extern Target TheARM64leTarget;
 extern Target TheARM64beTarget;
+extern Target TheAArch64leTarget;
+extern Target TheAArch64beTarget;
 
 MCCodeEmitter *createARM64MCCodeEmitter(const MCInstrInfo &MCII,
                                         const MCRegisterInfo &MRI,
diff --git a/llvm/lib/Target/ARM64/TargetInfo/ARM64TargetInfo.cpp b/llvm/lib/Target/ARM64/TargetInfo/ARM64TargetInfo.cpp
index c2b6f5c7045..247566825ab 100644
--- a/llvm/lib/Target/ARM64/TargetInfo/ARM64TargetInfo.cpp
+++ b/llvm/lib/Target/ARM64/TargetInfo/ARM64TargetInfo.cpp
@@ -14,6 +14,8 @@ using namespace llvm;
 namespace llvm {
 Target TheARM64leTarget;
 Target TheARM64beTarget;
+Target TheAArch64leTarget;
+Target TheAArch64beTarget;
 } // end namespace llvm
 
 extern "C" void LLVMInitializeARM64TargetInfo() {
@@ -21,4 +23,9 @@ extern "C" void LLVMInitializeARM64TargetInfo() {
                                                    "ARM64 (little endian)");
   RegisterTarget<Triple::arm64_be, /*HasJIT=*/true> Y(TheARM64beTarget, "arm64_be",
                                                       "ARM64 (big endian)");
+
+  RegisterTarget<Triple::aarch64, /*HasJIT=*/true> Z(
+      TheAArch64leTarget, "aarch64", "ARM64 (little endian)");
+  RegisterTarget<Triple::aarch64_be, /*HasJIT=*/true> W(
+      TheAArch64beTarget, "aarch64_be", "ARM64 (big endian)");
 }