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path: root/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
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* [ARM] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-111-249/+0
* [llvm-objdump] Implement -Mreg-names-raw/-std options.Igor Kudrin2019-02-261-1/+8
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [AArch64][ARM] Armv8.4-A: Trace synchronization barrier instructionSjoerd Meijer2018-07-061-0/+2
* [ARM] v8.3-a complex number supportSam Parker2017-09-291-0/+3
* [ARM] Fix some Include What You Use warnings; other minor fixes (NFC).Eugene Zelenko2017-02-031-1/+1
* ARM target does not use printAliasInstr machinery whichSjoerd Meijer2016-06-031-0/+6
* [ARM] Add ARMv8.2-A FP16 scalar instructionsOliver Stannard2016-01-251-0/+3
* Remove extra forward declarations and scrub includes for all in tree InstPrin...Craig Topper2015-12-251-3/+0
* Revert "[ARM] Add ARMv8.2-A FP16 scalar instructions"Reid Kleckner2015-12-161-3/+0
* [ARM] Add ARMv8.2-A FP16 scalar instructionsOliver Stannard2015-12-161-0/+3
* Remove unused MCSubtargetInfo argument from the ARM MCInstPrinter ctors.Eric Christopher2015-03-301-1/+1
* [ARM] Enable changing instprinter's behavior based on the per-functionAkira Hatanaka2015-03-271-74/+135
* clang-format ARMInstPrinter.{h,cpp} before I make changes to these files.Akira Hatanaka2015-03-271-8/+7
* [MCInstPrinter] Enable MCInstPrinter to change its behavior based on theAkira Hatanaka2015-03-271-1/+2
* Add support for ARM modified-immediate assembly syntax.Asiri Rathnayake2014-12-021-0/+1
* ARM: remove dead InstPrinting codeTim Northover2014-10-061-1/+0
* ARM: implement MRS/MSR (banked reg) system instructions.Tim Northover2014-08-151-0/+1
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-2/+2
* [C++11] Add 'override' keyword to virtual methods that override their base cl...Craig Topper2014-03-101-2/+2
* This corrects the implementation of Thumb ADR instruction. There are three i...Mihai Popa2013-07-031-0/+1
* ARM: add operands pre-writeback variants when neededAmaury de la Vieuville2013-06-181-0/+2
* ARM: ISB cannot be passed the same options as DMBAmaury de la Vieuville2013-06-101-0/+1
* ARM: Correct printing of pre-indexed operands.Quentin Colombet2013-04-121-2/+5
* Remove hard coded registers in ARM ldrexd and strexd instructionsWeiming Zhao2012-11-161-0/+1
* ARM: Better disassembly for pc-relative LDR.Jim Grosbach2012-10-301-1/+2
* Fix #13241, a bug around shift immediate operand for ARM instruction ADR.Jiangning Liu2012-08-021-0/+1
* Move getOpcodeName from the various target InstPrinters into the superclass M...Benjamin Kramer2012-04-021-1/+0
* Remove getInstructionName from MCInstPrinter implementations in favor of usin...Craig Topper2012-04-021-2/+0
* Make MCInstrInfo available to the MCInstPrinter. This will be used to remove ...Craig Topper2012-04-021-2/+2
* ARM refactor more NEON VLD/VST instructions to use composite physregsJim Grosbach2012-03-061-5/+3
* Tidy up. Kill some dead code.Jim Grosbach2012-03-061-1/+0
* ARM Refactor VLD/VST spaced pair instructions.Jim Grosbach2012-03-051-0/+2
* ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach2012-03-051-0/+1
* Make MCRegisterInfo available to the the MCInstPrinter.Jim Grosbach2012-03-051-1/+2
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,...Jia Liu2012-02-181-1/+1
* NEON VLD4(all lanes) assembly parsing and encoding.Jim Grosbach2012-01-251-0/+4
* NEON VLD3(all lanes) assembly parsing and encoding.Jim Grosbach2012-01-241-0/+4
* NEON VLD4(multiple 4 element structures) assembly parsing.Jim Grosbach2012-01-241-0/+2
* NEON VLD3(multiple 3-element structures) assembly parsing.Jim Grosbach2012-01-231-0/+2
* ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).Jim Grosbach2011-12-221-0/+2
* ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.Jim Grosbach2011-12-211-0/+2
* ARM NEON VST2 assembly parsing and encoding.Jim Grosbach2011-12-141-0/+2
* ARM parsing for VLD1 two register all lanes, no writeback.Jim Grosbach2011-11-301-0/+2
* ARM parsing aliases for VLD1 single register all lanes.Jim Grosbach2011-11-301-0/+2
* Assembly parsing for 4-register variant of VLD1.Jim Grosbach2011-10-211-0/+1
* Assembly parsing for 3-register variant of VLD1.Jim Grosbach2011-10-211-0/+1
* ARM VLD parsing and encoding.Jim Grosbach2011-10-211-0/+1
* ARM VTBL (one register) assembly parsing and encoding.Jim Grosbach2011-10-181-0/+1
* ARM parsing and encoding for the <option> form of LDC/STC instructions.Jim Grosbach2011-10-121-0/+1
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