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path: root/llvm/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
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* [ARM] Move InstPrinter files to MCTargetDesc. NFCRichard Trieu2019-05-111-249/+0
| | | | | | | | | For some targets, there is a circular dependency between InstPrinter and MCTargetDesc. Merging them together will fix this. For the other targets, the merging is to maintain consistency so all targets will have the same structure. llvm-svn: 360490
* [llvm-objdump] Implement -Mreg-names-raw/-std options.Igor Kudrin2019-02-261-1/+8
| | | | | | | | | | | | | | The --disassembler-options, or -M, are used to customize the disassembler and affect its output. The two implemented options allow selecting register names on ARM: * With -Mreg-names-raw, the disassembler uses rNN for all registers. * With -Mreg-names-std it prints sp, lr and pc for r13, r14 and r15, which is the default behavior of llvm-objdump. Differential Revision: https://reviews.llvm.org/D57680 llvm-svn: 354870
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
| | | | | | | | | | | | | | | | | to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
* [AArch64][ARM] Armv8.4-A: Trace synchronization barrier instructionSjoerd Meijer2018-07-061-0/+2
| | | | | | | | This adds the Armv8.4-A Trace synchronization barrier (TSB) instruction. Differential Revision: https://reviews.llvm.org/D48918 llvm-svn: 336418
* [ARM] v8.3-a complex number supportSam Parker2017-09-291-0/+3
| | | | | | | | | | | | | | | New instructions are added to AArch32 and AArch64 to aid floating-point multiplication and addition of complex numbers, where the complex numbers are packed in a vector register as a pair of elements. The Imaginary part of the number is placed in the more significant element, and the Real part of the number is placed in the less significant element. This patch adds assembler for the ARM target. Differential Revision: https://reviews.llvm.org/D36789 llvm-svn: 314511
* [ARM] Fix some Include What You Use warnings; other minor fixes (NFC).Eugene Zelenko2017-02-031-1/+1
| | | | | | This is preparation to reduce MCExpr.h dependencies. llvm-svn: 294052
* ARM target does not use printAliasInstr machinery whichSjoerd Meijer2016-06-031-0/+6
| | | | | | | | | | | | | | | | | | forces having special checks in ArmInstPrinter::printInstruction. This patch addresses this issue. Not all special checks could be removed: either they involve elaborated conditions under which the alias is emitted (e.g. ldm/stm on sp may be pop/push but only if the number of registers is >= 2) or the number of registers is multivalued (like happens again with ldm/stm) and they do not match the InstAlias pattern which assumes single-valued operands in the pattern. Patch by: Roger Ferrer Ibanez Differential Revision: http://reviews.llvm.org/D20237 llvm-svn: 271667
* [ARM] Add ARMv8.2-A FP16 scalar instructionsOliver Stannard2016-01-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This was originally committed as r255762, but reverted as it broke windows bots. Re-commitiing the exact same patch, as the underlying cause was fixed by r258677. ARMv8.2-A adds 16-bit floating point versions of all existing VFP floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. The assembly for these instructions uses S registers (AArch32 does not have H registers), but the instructions have ".f16" type specifiers rather than ".f32" or ".f64". The top 16 bits of each source register are ignored, and the top 16 bits of the destination register are set to zero. These instructions are mostly the same as the 32- and 64-bit versions, but they use coprocessor 9 rather than 10 and 11. Two new instructions, VMOVX and VINS, have been added to allow packing and extracting two 16-bit floats stored in the top and bottom halves of an S register. New fixup kinds have been added for the PC-relative load and store instructions, but no ELF relocations have been added as they have a range of 512 bytes. Differential Revision: http://reviews.llvm.org/D15038 llvm-svn: 258678
* Remove extra forward declarations and scrub includes for all in tree ↵Craig Topper2015-12-251-3/+0
| | | | | | InstPrinters. NFC llvm-svn: 256427
* Revert "[ARM] Add ARMv8.2-A FP16 scalar instructions"Reid Kleckner2015-12-161-3/+0
| | | | | | This reverts commit r255762. llvm-svn: 255806
* [ARM] Add ARMv8.2-A FP16 scalar instructionsOliver Stannard2015-12-161-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | ARMv8.2-A adds 16-bit floating point versions of all existing VFP floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. The assembly for these instructions uses S registers (AArch32 does not have H registers), but the instructions have ".f16" type specifiers rather than ".f32" or ".f64". The top 16 bits of each source register are ignored, and the top 16 bits of the destination register are set to zero. These instructions are mostly the same as the 32- and 64-bit versions, but they use coprocessor 9 rather than 10 and 11. Two new instructions, VMOVX and VINS, have been added to allow packing and extracting two 16-bit floats stored in the top and bottom halves of an S register. New fixup kinds have been added for the PC-relative load and store instructions, but no ELF relocations have been added as they have a range of 512 bytes. Differential Revision: http://reviews.llvm.org/D15038 llvm-svn: 255762
* Remove unused MCSubtargetInfo argument from the ARM MCInstPrinter ctors.Eric Christopher2015-03-301-1/+1
| | | | llvm-svn: 233609
* [ARM] Enable changing instprinter's behavior based on the per-functionAkira Hatanaka2015-03-271-74/+135
| | | | | | subtarget. llvm-svn: 233451
* clang-format ARMInstPrinter.{h,cpp} before I make changes to these files.Akira Hatanaka2015-03-271-8/+7
| | | | llvm-svn: 233448
* [MCInstPrinter] Enable MCInstPrinter to change its behavior based on theAkira Hatanaka2015-03-271-1/+2
| | | | | | | | | | | | | | | | | | | | per-function subtarget. Currently, code-gen passes the default or generic subtarget to the constructors of MCInstPrinter subclasses (see LLVMTargetMachine::addPassesToEmitFile), which enables some targets (AArch64, ARM, and X86) to change their instprinter's behavior based on the subtarget feature bits. Since the backend can now use different subtargets for each function, instprinter has to be changed to use the per-function subtarget rather than the default subtarget. This patch takes the first step towards enabling instprinter to change its behavior based on the per-function subtarget. It adds a bit "PassSubtarget" to AsmWriter which tells table-gen to pass a reference to MCSubtargetInfo to the various print methods table-gen auto-generates. I will follow up with changes to instprinters of AArch64, ARM, and X86. llvm-svn: 233411
* Add support for ARM modified-immediate assembly syntax.Asiri Rathnayake2014-12-021-0/+1
| | | | | | | | | | | | | | | | | | | | Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. llvm-svn: 223113
* ARM: remove dead InstPrinting codeTim Northover2014-10-061-1/+0
| | | | | | | This instruction form is handled by different AsmOperands now, so the code is completely dead (and wrong anyway). llvm-svn: 219127
* ARM: implement MRS/MSR (banked reg) system instructions.Tim Northover2014-08-151-0/+1
| | | | | | | | | | These are system-only instructions for CPUs with virtualization extensions, allowing a hypervisor easy access to all of the various different AArch32 registers. rdar://problem/17861345 llvm-svn: 215700
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-2/+2
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-101-2/+2
| | | | | | class. llvm-svn: 203433
* This corrects the implementation of Thumb ADR instruction. There are three ↵Mihai Popa2013-07-031-0/+1
| | | | | | | | | | issues: 1. it should accept only 4-byte aligned addresses 2. the maximum offset should be 1020 3. it should be encoded with the offset scaled by two bits llvm-svn: 185528
* ARM: add operands pre-writeback variants when neededAmaury de la Vieuville2013-06-181-0/+2
| | | | llvm-svn: 184181
* ARM: ISB cannot be passed the same options as DMBAmaury de la Vieuville2013-06-101-0/+1
| | | | | | ISB should only accepts full system sync, other options are reserved llvm-svn: 183656
* ARM: Correct printing of pre-indexed operands.Quentin Colombet2013-04-121-2/+5
| | | | | | | | | | | | | According to the ARM reference manual, constant offsets are mandatory for pre-indexed addressing modes. The MC disassembler was not obeying this when the offset is 0. It was producing instructions like: str r0, [r1]!. Correct syntax is: str r0, [r1, #0]!. This change modifies the dumping of operands so that the offset is always printed, regardless of its value, when pre-indexed addressing mode is used. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179398
* Remove hard coded registers in ARM ldrexd and strexd instructionsWeiming Zhao2012-11-161-0/+1
| | | | | | | | | This patch replaces the hard coded GPR pair [R0, R1] of Intrinsic:arm_ldrexd and [R2, R3] of Intrinsic:arm_strexd with even/odd GPRPair reg class. Similar to the lowering of atomic_64 operation. llvm-svn: 168207
* ARM: Better disassembly for pc-relative LDR.Jim Grosbach2012-10-301-1/+2
| | | | | | | | | When the operand is a plain immediate rather than a label, print it as [pc, #imm] like we do for the Thumb2 wide encoding variant. rdar://12154503 llvm-svn: 166991
* Fix #13241, a bug around shift immediate operand for ARM instruction ADR.Jiangning Liu2012-08-021-0/+1
| | | | llvm-svn: 161159
* Move getOpcodeName from the various target InstPrinters into the superclass ↵Benjamin Kramer2012-04-021-1/+0
| | | | | | | | MCInstPrinter. All implementations used the same code. llvm-svn: 153866
* Remove getInstructionName from MCInstPrinter implementations in favor of ↵Craig Topper2012-04-021-2/+0
| | | | | | using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations. llvm-svn: 153863
* Make MCInstrInfo available to the MCInstPrinter. This will be used to remove ↵Craig Topper2012-04-021-2/+2
| | | | | | getInstructionName and the static data it contains since the same tables are already in MCInstrInfo. llvm-svn: 153860
* ARM refactor more NEON VLD/VST instructions to use composite physregsJim Grosbach2012-03-061-5/+3
| | | | | | | Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the pseudos as a result. llvm-svn: 152150
* Tidy up. Kill some dead code.Jim Grosbach2012-03-061-1/+0
| | | | llvm-svn: 152131
* ARM Refactor VLD/VST spaced pair instructions.Jim Grosbach2012-03-051-0/+2
| | | | | | Use the new composite physical registers. llvm-svn: 152063
* ARM refactor away a bunch of VLD/VST pseudo instructions.Jim Grosbach2012-03-051-0/+1
| | | | | | | | | With the new composite physical registers to represent arbitrary pairs of DPR registers, we don't need the pseudo-registers anymore. Get rid of a bunch of them that use DPR register pairs and just use the real instructions directly instead. llvm-svn: 152045
* Make MCRegisterInfo available to the the MCInstPrinter.Jim Grosbach2012-03-051-1/+2
| | | | | | | Used to allow context sensitive printing of super-register or sub-register references. llvm-svn: 152043
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
* NEON VLD4(all lanes) assembly parsing and encoding.Jim Grosbach2012-01-251-0/+4
| | | | llvm-svn: 148884
* NEON VLD3(all lanes) assembly parsing and encoding.Jim Grosbach2012-01-241-0/+4
| | | | llvm-svn: 148882
* NEON VLD4(multiple 4 element structures) assembly parsing.Jim Grosbach2012-01-241-0/+2
| | | | llvm-svn: 148762
* NEON VLD3(multiple 3-element structures) assembly parsing.Jim Grosbach2012-01-231-0/+2
| | | | llvm-svn: 148745
* ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).Jim Grosbach2011-12-221-0/+2
| | | | | | rdar://10558523 llvm-svn: 147189
* ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.Jim Grosbach2011-12-211-0/+2
| | | | llvm-svn: 147025
* ARM NEON VST2 assembly parsing and encoding.Jim Grosbach2011-12-141-0/+2
| | | | | | | | Work in progress. Parsing for non-writeback, single spaced register lists works now. The rest have the representations better factored, but still need more to be able to parse properly. llvm-svn: 146579
* ARM parsing for VLD1 two register all lanes, no writeback.Jim Grosbach2011-11-301-0/+2
| | | | llvm-svn: 145504
* ARM parsing aliases for VLD1 single register all lanes.Jim Grosbach2011-11-301-0/+2
| | | | llvm-svn: 145464
* Assembly parsing for 4-register variant of VLD1.Jim Grosbach2011-10-211-0/+1
| | | | llvm-svn: 142682
* Assembly parsing for 3-register variant of VLD1.Jim Grosbach2011-10-211-0/+1
| | | | llvm-svn: 142675
* ARM VLD parsing and encoding.Jim Grosbach2011-10-211-0/+1
| | | | | | | | | | | | Next step in the ongoing saga of NEON load/store assmebly parsing. Handle VLD1 instructions that take a two-register register list. Adjust the instruction definitions to only have the single encoded register as an operand. The super-register from the pseudo is kept as an implicit def, so passes which come after pseudo-expansion still know that the instruction defines the other subregs. llvm-svn: 142670
* ARM VTBL (one register) assembly parsing and encoding.Jim Grosbach2011-10-181-0/+1
| | | | llvm-svn: 142441
* ARM parsing and encoding for the <option> form of LDC/STC instructions.Jim Grosbach2011-10-121-0/+1
| | | | llvm-svn: 141786
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