| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| ... | |
| * | Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset ... | Jiangning Liu | 2012-08-02 | 1 | -3/+8 |
| * | Fix #13138, a bug around ARM instruction DSB encoding and decoding issue. | Jiangning Liu | 2012-08-02 | 1 | -12/+1 |
| * | Fix a typo (the the => the) | Sylvestre Ledru | 2012-07-23 | 1 | -1/+1 |
| * | Fix instruction description of VMOV (between two ARM core registers and two s... | Richard Barton | 2012-07-10 | 1 | -4/+4 |
| * | Revert r159938 (and r159945) to appease the buildbots. | Chad Rosier | 2012-07-09 | 1 | -4/+4 |
| * | Oops - correct broken disassembly for VMOV | Richard Barton | 2012-07-09 | 1 | -1/+1 |
| * | Fix instruction description of VMOV (between two ARM core registers and two s... | Richard Barton | 2012-07-09 | 1 | -4/+4 |
| * | Correct decoder for T1 conditional B encoding | Richard Barton | 2012-06-06 | 1 | -2/+2 |
| * | ARMDisassembler.cpp: Fix utf8 char in comments. | NAKAMURA Takumi | 2012-05-22 | 1 | -3/+3 |
| * | Tweak to the fix in r156212, as with the change in removing the shift the | Kevin Enderby | 2012-05-04 | 1 | -1/+1 |
| * | Fix a bug in the ARM disassembler for wide branch conditional instructions | Kevin Enderby | 2012-05-04 | 1 | -1/+1 |
| * | Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits | Kevin Enderby | 2012-05-03 | 1 | -4/+34 |
| * | Fixed disassembler for vstm/vldm ARM VFP instructions. | Silviu Baranga | 2012-05-03 | 1 | -4/+6 |
| * | ARM: Tweak tADDrSP definition for consistent operand order. | Jim Grosbach | 2012-04-27 | 1 | -1/+1 |
| * | Refactor IT handling not to store the bottom bit of the condition code in the... | Richard Barton | 2012-04-27 | 1 | -8/+3 |
| * | Refactor Thumb ITState handling in ARM Disassembler to more efficiently use i... | Richard Barton | 2012-04-24 | 1 | -31/+69 |
| * | Added support for disassembling unpredictable swp/swpb ARM instructions. | Silviu Baranga | 2012-04-18 | 1 | -0/+4 |
| * | Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the ... | Silviu Baranga | 2012-04-18 | 1 | -0/+30 |
| * | Fix ARM disassembly of VLD2 (single 2-element structure to all lanes) | Kevin Enderby | 2012-04-17 | 1 | -7/+1 |
| * | Fix a few more places in the ARM disassembler so that branches get | Kevin Enderby | 2012-04-12 | 1 | -4/+29 |
| * | Fixed a case of ARM disassembly getting an assert on a bad encoding | Kevin Enderby | 2012-04-11 | 1 | -0/+2 |
| * | Fix ARM disassembly of VLD instructions with writebacks. And add test a case | Kevin Enderby | 2012-04-11 | 1 | -0/+12 |
| * | ARMDisassembler: drop bogus dependency on ARMCodeGen | Dylan Noblesmith | 2012-04-03 | 1 | -2/+1 |
| * | Remove unnecessary llvm:: qualifications | Craig Topper | 2012-03-27 | 1 | -209/+209 |
| * | Added soft fail checks for the disassembler when decoding some corner cases o... | Silviu Baranga | 2012-03-22 | 1 | -1/+81 |
| * | Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDR... | Silviu Baranga | 2012-03-22 | 1 | -3/+31 |
| * | Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test | Kevin Enderby | 2012-03-21 | 1 | -0/+19 |
| * | The ARM instructions that have an unpredictable behavior when the pc register... | Silviu Baranga | 2012-03-20 | 1 | -2/+8 |
| * | Use uint16_t to store registers and opcode in static tables in the target spe... | Craig Topper | 2012-03-11 | 1 | -6/+6 |
| * | Tidy up. Remove dead code that slipped into previous commit. | Jim Grosbach | 2012-03-07 | 1 | -6/+0 |
| * | ARM more NEON VLD/VST composite physical register refactoring. | Jim Grosbach | 2012-03-06 | 1 | -0/+7 |
| * | ARM refactor more NEON VLD/VST instructions to use composite physregs | Jim Grosbach | 2012-03-06 | 1 | -25/+41 |
| * | Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction. | Kevin Enderby | 2012-03-06 | 1 | -7/+7 |
| * | ARM Refactor VLD/VST spaced pair instructions. | Jim Grosbach | 2012-03-05 | 1 | -0/+50 |
| * | ARM refactor away a bunch of VLD/VST pseudo instructions. | Jim Grosbach | 2012-03-05 | 1 | -6/+89 |
| * | Make MemoryObject accessor members const again | Derek Schuff | 2012-02-29 | 1 | -4/+4 |
| * | Fix the symbolic operand added for the C disassmbler API for the ARM bl | Kevin Enderby | 2012-02-27 | 1 | -1/+1 |
| * | Updated the llvm-mc disassembler C API to support for the X86 target. | Kevin Enderby | 2012-02-23 | 1 | -33/+35 |
| * | Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430,... | Jia Liu | 2012-02-18 | 1 | -1/+1 |
| * | Make the EDis tables const. | Benjamin Kramer | 2012-02-11 | 1 | -4/+4 |
| * | Convert assert(0) to llvm_unreachable | Craig Topper | 2012-02-07 | 1 | -1/+1 |
| * | Enable streaming of bitcode | Derek Schuff | 2012-02-06 | 1 | -4/+4 |
| * | More dead code removal (using -Wunreachable-code) | David Blaikie | 2012-01-20 | 1 | -1/+1 |
| * | ARM NEON VTBL/VTBX assembly parsing and encoding. | Jim Grosbach | 2011-12-15 | 1 | -4/+1 |
| * | ARM NEON refactor VST2 w/ writeback instructions. | Jim Grosbach | 2011-12-14 | 1 | -9/+18 |
| * | ARM NEON VST2 assembly parsing and encoding. | Jim Grosbach | 2011-12-14 | 1 | -30/+0 |
| * | ARM assembly parsing and encoding for VLD2 with writeback. | Jim Grosbach | 2011-12-09 | 1 | -9/+18 |
| * | Remove unused variable | Matt Beaumont-Gay | 2011-11-30 | 1 | -2/+0 |
| * | ARM parsing for VLD1 all lanes, with writeback. | Jim Grosbach | 2011-11-30 | 1 | -10/+6 |
| * | ARM assembly parsing and encoding for four-register VST1. | Jim Grosbach | 2011-11-29 | 1 | -28/+8 |
