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| author | Jim Grosbach <grosbach@apple.com> | 2011-12-09 21:28:25 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-12-09 21:28:25 +0000 |
| commit | d146a02c7969f3f0a8d6fb9b8a7a4c0be58cab8b (patch) | |
| tree | 410d661350359adf0779bdbe1b6865907dff9d82 /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | f5b32e52db9c08e6d4a4ca80f9eb946d92b7d55b (diff) | |
| download | bcm5719-llvm-d146a02c7969f3f0a8d6fb9b8a7a4c0be58cab8b.tar.gz bcm5719-llvm-d146a02c7969f3f0a8d6fb9b8a7a4c0be58cab8b.zip | |
ARM assembly parsing and encoding for VLD2 with writeback.
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
llvm-svn: 146278
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 27 |
1 files changed, 18 insertions, 9 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 0107f288b16..ae18decc53e 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -2085,15 +2085,24 @@ static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn, case ARM::VLD1d32Qwb_register: case ARM::VLD1d64Qwb_fixed: case ARM::VLD1d64Qwb_register: - case ARM::VLD2d8_UPD: - case ARM::VLD2d16_UPD: - case ARM::VLD2d32_UPD: - case ARM::VLD2q8_UPD: - case ARM::VLD2q16_UPD: - case ARM::VLD2q32_UPD: - case ARM::VLD2b8_UPD: - case ARM::VLD2b16_UPD: - case ARM::VLD2b32_UPD: + case ARM::VLD2d8wb_fixed: + case ARM::VLD2d16wb_fixed: + case ARM::VLD2d32wb_fixed: + case ARM::VLD2q8wb_fixed: + case ARM::VLD2q16wb_fixed: + case ARM::VLD2q32wb_fixed: + case ARM::VLD2d8wb_register: + case ARM::VLD2d16wb_register: + case ARM::VLD2d32wb_register: + case ARM::VLD2q8wb_register: + case ARM::VLD2q16wb_register: + case ARM::VLD2q32wb_register: + case ARM::VLD2b8wb_fixed: + case ARM::VLD2b16wb_fixed: + case ARM::VLD2b32wb_fixed: + case ARM::VLD2b8wb_register: + case ARM::VLD2b16wb_register: + case ARM::VLD2b32wb_register: case ARM::VLD3d8_UPD: case ARM::VLD3d16_UPD: case ARM::VLD3d32_UPD: |
