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path: root/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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* Allow only disassembling of M-class MSR masks that the assembler knows how ↵James Molloy2014-08-011-1/+47
| | | | | | | | | | to assemble back. Note: The current code in DecodeMSRMask() rejects the unpredictable A/R MSR mask '0000' with Fail. The code in the patch follows this style and rejects unpredictable M-class MSR masks also with Fail (instead of SoftFail). If SoftFail is preferred in this case then additional changes to ARMInstPrinter (to print non-symbolic masks) and ARMAsmParser (to parse non-symbolic masks) will be needed. Patch by Petr Pavlu! llvm-svn: 214505
* [Modules] Fix potential ODR violations by sinking the DEBUG_TYPEChandler Carruth2014-04-221-2/+2
| | | | | | | definition below all of the header #include lines, lib/Target/... edition. llvm-svn: 206842
* [MC] Require an MCContext when constructing an MCDisassembler.Lang Hames2014-04-151-8/+12
| | | | | | | | | | | | | | | | This patch re-introduces the MCContext member that was removed from MCDisassembler in r206063, and requires that an MCContext be passed in at MCDisassembler construction time. (Previously the MCContext member had been initialized in an ad-hoc fashion after construction). The MCCContext member can be used by MCDisassembler sub-classes to construct constant or target-specific MCExprs. This patch updates disassemblers for in-tree targets, and provides the MCRegisterInfo instance that some disassemblers were using through the MCContext (previously those backends were constructing their own MCRegisterInfo instances). llvm-svn: 206241
* ARM: rename ARMle/ARMbe with ARMLE/ARMBE, and Thumble/Thumbbe with ↵Christian Pirker2014-04-011-4/+4
| | | | | | ThumbLE/ThumbBE llvm-svn: 205317
* Add ARM big endian Target (armeb, thumbeb)Christian Pirker2014-03-281-2/+6
| | | | | | Reviewed at http://llvm-reviews.chandlerc.com/D3095 llvm-svn: 205007
* [C++11] Add 'override' keyword to virtual methods that override their base ↵Craig Topper2014-03-101-10/+6
| | | | | | class. llvm-svn: 203439
* [ARM] Handling for coprocessor instructions that are undefined starting from ↵Artyom Skrobov2013-11-081-0/+10
| | | | | | ARMv8 (ARM encodings) llvm-svn: 194261
* [ARM] NEON instructions were erroneously decoded from certain invalid encodingsArtyom Skrobov2013-10-301-20/+20
| | | | llvm-svn: 193705
* ARM: provide diagnostics on more writeback LDM/STM instructionsTim Northover2013-10-221-14/+16
| | | | | | | | | | | | | | The set of circumstances where the writeback register is allowed to be in the list of registers is rather baroque, but I think this implements them all on the assembly parsing side. For disassembly, we still warn about an ARM-mode LDM even if the architecture revision is < v7 (the required architecture information isn't available). It's a silly instruction anyway, so hopefully no-one will mind. rdar://problem/15223374 llvm-svn: 193185
* [ARM] Remove an unused function from the disassembler.Joey Gouly2013-10-011-11/+0
| | | | | | Pointed out by Joerg. llvm-svn: 191749
* [ARMv8] Add support for the v8 cryptography extensions.Amara Emerson2013-09-191-0/+20
| | | | llvm-svn: 190996
* This corrects creation of operands for t2PLDW. It also removes the ↵Mihai Popa2013-08-061-0/+2
| | | | | | | | definition of t2PLDWpci, as pldw does not have a literal variant (i.e. pc relative version) llvm-svn: 187804
* [ARMv8] Add support for the NEON instructions vmaxnm/vminnm.Joey Gouly2013-07-171-0/+18
| | | | | | | This adds a new class for non-predicable NEON instructions and a new DecoderNamespace for v8 NEON instructions. llvm-svn: 186504
* Remove an unneeded call to 'UpdateThumbVFPPredicate', spotted by Amaury.Joey Gouly2013-07-041-1/+0
| | | | llvm-svn: 185651
* Add support for MC assembling and disassembling of vsel{ge, gt, eq, vs} ↵Joey Gouly2013-07-041-0/+15
| | | | | | | | | instructions. This adds a new decoder table/namespace 'VFPV8', as these instructions have their top 4 bits as 0b1111, while other Thumb instructions have 0b1110. llvm-svn: 185642
* ARM: check predicate bits for thumb instructionsAmaury de la Vieuville2013-06-241-13/+17
| | | | | | | When encoded to thumb, VFP instruction and VMOV/VDUP between scalar and core registers, must have their predicate bit to 0b1110. llvm-svn: 184707
* ARM: rGPR is meant to be unpredictable, not undefinedAmaury de la Vieuville2013-06-241-2/+5
| | | | llvm-svn: 184706
* ARM: fix IT decodingAmaury de la Vieuville2013-06-241-4/+2
| | | | | | mask == 0 -> UNPRED llvm-svn: 184702
* ARM: enable decoding of pc-relative PLD/PLIAmaury de la Vieuville2013-06-241-36/+115
| | | | llvm-svn: 184701
* ARM: fix thumb literal loads decodingAmaury de la Vieuville2013-06-181-18/+205
| | | | | | | | This fixes two previous issues: - Negative offsets were not correctly disassembled - The decoded opcodes were not the right one llvm-svn: 184180
* ARM: thumb stores cannot use PC as dest registerAmaury de la Vieuville2013-06-181-0/+37
| | | | llvm-svn: 184179
* ARM: fix B decodingAmaury de la Vieuville2013-06-131-1/+1
| | | | llvm-svn: 183914
* ARM: Enforce decoding rules for VLDn instructionsAmaury de la Vieuville2013-06-111-28/+36
| | | | llvm-svn: 183731
* ARM: Fix STREX/LDREX reecodingAmaury de la Vieuville2013-06-111-10/+28
| | | | | | The decoded MCInst wasn't reencoded as the same instruction llvm-svn: 183729
* ARM: ISB cannot be passed the same options as DMBAmaury de la Vieuville2013-06-101-0/+11
| | | | | | ISB should only accepts full system sync, other options are reserved llvm-svn: 183656
* ARM: fix VMOVvnf32 decoding when ambiguous with VCVTAmaury de la Vieuville2013-06-081-0/+4
| | | | | | Enforce Table A7-15 (op=1, cmode=0b111) -> UNDEF llvm-svn: 183612
* ARM: enforce SRS decoding constraintsAmaury de la Vieuville2013-06-081-1/+7
| | | | llvm-svn: 183611
* ARM: fix CPS decoding when ambiguous with QADDAmaury de la Vieuville2013-06-081-0/+32
| | | | | | | | | Handle the case when the disassembler table can't tell the difference between some encodings of QADD and CPS. Add some necessary safe guards in CPS decoding as well. llvm-svn: 183610
* ARM: fix VCVT decodingAmaury de la Vieuville2013-06-081-2/+2
| | | | | | UNPRED was reported instead of UNDEF llvm-svn: 183608
* ARM: add fstmx and fldmx instructions for assemblyTim Northover2013-05-311-2/+15
| | | | | | | | | These instructions are deprecated oddities, but we still need to be able to disassemble (and reassemble) them if and when they're encountered. Patch by Amaury de la Vieuville. llvm-svn: 183011
* Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.Michael J. Spencer2013-05-241-1/+1
| | | | llvm-svn: 182680
* Remove the Copied parameter from MemoryObject::readBytes.Benjamin Kramer2013-05-241-3/+3
| | | | | | | | | | There was exactly one caller using this API right, the others were relying on specific behavior of the default implementation. Since it's too hard to use it right just remove it and standardize on the default behavior. Defines away PR16132. llvm-svn: 182636
* Add MCSymbolizer for symbolic/annotated disassembly.Ahmed Bougacha2013-05-241-107/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a basic first step towards symbolization of disassembled instructions. This used to be done using externally provided (C API) callbacks. This patch introduces: - the MCSymbolizer class, that mimics the same functions that were used in the X86 and ARM disassemblers to symbolize immediate operands and to annotate loads based off PC (for things like c string literals). - the MCExternalSymbolizer class, which implements the old C API. - the MCRelocationInfo class, which provides a way for targets to translate relocations (either object::RelocationRef, or disassembler C API VariantKinds) to MCExprs. - the MCObjectSymbolizer class, which does symbolization using what it finds in an object::ObjectFile. This makes simple symbolization (with no fancy relocation stuff) work for all object formats! - x86-64 Mach-O and ELF MCRelocationInfos. - A basic ARM Mach-O MCRelocationInfo, that provides just enough to support the C API VariantKinds. Most of what works in otool (the only user of the old symbolization API that I know of) for x86-64 symbolic disassembly (-tvV) works, namely: - symbol references: call _foo; jmp 15 <_foo+50> - relocations: call _foo-_bar; call _foo-4 - __cf?string: leaq 193(%rip), %rax ## literal pool for "hello" Stub support is the main missing part (because libObject doesn't know, among other things, about mach-o indirect symbols). As for the MCSymbolizer API, instead of relying on the disassemblers to call the tryAdding* methods, maybe this could be done automagically using InstrInfo? For instance, even though PC-relative LEAs are used to get the address of string literals in a typical Mach-O file, a MOV would be used in an ELF file. And right now, the explicit symbolization only recognizes PC-relative LEAs. InstrInfo should have already have most of what is needed to know what to symbolize, so this can definitely be improved. I'd also like to remove object::RelocationRef::getValueString (it seems only used by relocation printing in objdump), as simply printing the created MCExpr is definitely enough (and cleaner than string concats). llvm-svn: 182625
* VSTn instructions have a number of encoding constraints which are not ↵Mihai Popa2013-05-201-0/+51
| | | | | | implemented. I have added these using wrapper methods around the original custom decoder (incidentally - this is a huge poorly written method that should be cleaned up. I have left it as is since the changes would be much to hard to review). llvm-svn: 182281
* Q registers are encoded in fields of the same length as D registers. As Q ↵Mihai Popa2013-05-201-1/+1
| | | | | | registers are half as many, the ARM reference manual mandates the least significant bit to be zeroed out. Failure to do so should result in an undefined instruction. With this change test/MC/Disassembler/ARM/invalid-VQADD-arm.txt is passing (removed XFAIL). llvm-svn: 182279
* Replace some bit operations with simpler ones. No functionality change.Benjamin Kramer2013-05-191-1/+1
| | | | llvm-svn: 182226
* The purpose of the patch is to fix the syntax of ARM mrc and mrc2 ↵Mihai Popa2013-05-131-0/+18
| | | | | | instructions when they are used to write to the APSR. In this case, the destination operand should be APSR_nzcv, and the encoding of the target should be 0b1111 (same as for PC). In pre-UAL syntax, this form used the PC register as a textual target. This is still allowed for backward compatibility. llvm-svn: 181705
* ARM: Fix encoding of hint instruction for Thumb.Quentin Colombet2013-04-261-4/+6
| | | | | | | | | | | | | | | "hint" space for Thumb actually overlaps the encoding space of the CPS instruction. In actuality, hints can be defined as CPS instructions where imod and M bits are all nil. Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe, sev) in DecodeT2CPSInstruction. This commit adds a proper diagnostic message for Imm0_4 and updates all tests. Patch by Mihail Popa <Mihail.Popa@arm.com>. llvm-svn: 180617
* ARM: Permit "sp" in ARM variant of STREXD instructionsTim Northover2013-04-191-1/+1
| | | | | | Patch from Mihail Popa llvm-svn: 179854
* ARM: permit "sp" in ARM variants of MOVW/MOVT instructionsTim Northover2013-04-191-2/+3
| | | | llvm-svn: 179847
* Fix treatment of ARM unallocated hint instructions.Quentin Colombet2013-04-171-0/+11
| | | | | | | | | | | | | | | The reference manual defines only 5 permitted values for the immediate field of the "hint" instruction: 1. nop (imm == 0) 2. yield (imm == 1) 3. wfe (imm == 2) 4. wfi (imm == 3) 5. sev (imm == 4) Therefore, restrict the permitted values for the "hint" instruction to 0 through 4. Patch by Mihail Popa <Mihail.Popa@arm.com> llvm-svn: 179707
* Fix issue with disassembler decoding CBZ/CBNZ immediates as negatives when ↵Gordon Keiser2013-03-281-2/+2
| | | | | | | | the upper bit is set. They should always be zero-extended, not sign extended. Added test case. llvm-svn: 178275
* Patch by Gordon Keiser!Joe Abbey2013-03-261-1/+1
| | | | | | | | | | If PC or SP is the destination, the disassembler erroneously failed with the invalid encoding, despite the manual saying that both are fine. This patch addresses failure to decode encoding T4 of LDR (A8.8.62) which is a postindexed load, where the offset 0xc is applied to SP after the load occurs. llvm-svn: 178017
* Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky2012-12-191-16/+0
| | | | llvm-svn: 170578
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-6/+6
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
* Fixed the arm disassembly of invalid BFI instructions to not build a bad MCInstKevin Enderby2012-11-291-1/+7
| | | | | | which would then cause an assert when printed. rdar://11437956 llvm-svn: 168960
* Fix ARM's b.w instruction for thumb 2 and the encoding T4. The branch targetKevin Enderby2012-10-291-9/+21
| | | | | | | is 24 bits not 20 and the decoding needed to correctly handle converting the J1 and J2 bits to their I1 and I2 values to reconstruct the displacement. llvm-svn: 166982
* Fix a bug where a 32-bit address with the high bit does not get symbolicatedKevin Enderby2012-10-181-2/+3
| | | | | | | because the value is incorrectly being signed extended when passed to SymbolLookUp(). llvm-svn: 166234
* Fix the handling of edge cases in ARM shifted operands.Tim Northover2012-09-221-0/+5
| | | | | | | | | This patch fixes load/store instructions to handle less common cases like "asr #32", "rrx" properly throughout the MC layer. Patch by Chris Lidbury. llvm-svn: 164455
* Diagnose invalid alignments on duplicating VLDn instructions.Tim Northover2012-09-061-0/+4
| | | | | | Patch by Chris Lidbury. llvm-svn: 163323
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