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| author | Tim Northover <Tim.Northover@arm.com> | 2013-04-19 09:58:09 +0000 |
|---|---|---|
| committer | Tim Northover <Tim.Northover@arm.com> | 2013-04-19 09:58:09 +0000 |
| commit | a155ab2dd2290f3571853038c8495026160659cd (patch) | |
| tree | b431760c56379e54bbbba4adac7bfea5d519705c /llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | |
| parent | 3976656e08c33f4709b5b7b595de92c64559a9cd (diff) | |
| download | bcm5719-llvm-a155ab2dd2290f3571853038c8495026160659cd.tar.gz bcm5719-llvm-a155ab2dd2290f3571853038c8495026160659cd.zip | |
ARM: permit "sp" in ARM variants of MOVW/MOVT instructions
llvm-svn: 179847
Diffstat (limited to 'llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 9c81eceb40f..631168b1539 100644 --- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -1998,9 +1998,10 @@ static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, imm |= (fieldFromInstruction(Insn, 16, 4) << 12); if (Inst.getOpcode() == ARM::MOVTi16) - if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; - if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) + + if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) return MCDisassembler::Fail; if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) |
