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* Move some more instruction creation methods from RegisterInfo into InstrInfo.Owen Anderson2008-01-011-0/+128
| | | | llvm-svn: 45484
* Fix a problem where lib/Target/TargetInstrInfo.h would include and useChris Lattner2008-01-011-1/+1
| | | | | | | | | | a header file from libcodegen. This violates a layering order: codegen depends on target, not the other way around. The fix to this is to split TII into two classes, TII and TargetInstrInfoImpl, which defines stuff that depends on libcodegen. It is defined in libcodegen, where the base is not. llvm-svn: 45475
* Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of theOwen Anderson2007-12-311-0/+38
| | | | | | Machine-level API cleanup instigated by Chris. llvm-svn: 45470
* Add new shorter predicates for testing machine operands for various types: Chris Lattner2007-12-301-12/+12
| | | | | | | | | | | | e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on switching everything over, so new clients should just start using the shorter names. Remove old long accessors, switching everything over to use the short accessor: getMachineBasicBlock() -> getMBB(), getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc. llvm-svn: 45464
* Use MachineOperand::getImm instead of MachineOperand::getImmedValue. ↵Chris Lattner2007-12-301-10/+10
| | | | | | Likewise setImmedValue -> setImm llvm-svn: 45453
* use simplified operand addition methods.Chris Lattner2007-12-301-2/+2
| | | | llvm-svn: 45437
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+1
| | | | llvm-svn: 45418
* Remove isReg, isImm, and isMBB, and change all their users to use Dan Gohman2007-09-141-3/+3
| | | | | | | isRegister, isImmediate, and isMachineBasicBlock, which are equivalent, and more popular. llvm-svn: 41958
* Add lengthof and endof templates that hide a lot of sizeof computations.Owen Anderson2007-09-071-1/+2
| | | | | | Patch by Sterling Stein! llvm-svn: 41758
* ARM: make branch folder remove unconditional branchesDale Johannesen2007-07-121-2/+13
| | | | | | | | following jump tables that it earlier inserted. This would be OK on other targets but is needed for correctness only on ARM (constant islands needs to find jump tables). llvm-svn: 39782
* Remove clobbersPred. Add an OptionalDefOperand to instructions which have ↵Evan Cheng2007-07-101-5/+29
| | | | | | the 's' bit. llvm-svn: 38501
* Incorrect check.Evan Cheng2007-07-061-4/+2
| | | | llvm-svn: 37962
* Reflects the chanegs made to PredicateOperand.Evan Cheng2007-07-051-4/+10
| | | | llvm-svn: 37898
* Revert the earlier change that removed the M_REMATERIALIZABLE machineDan Gohman2007-06-261-14/+0
| | | | | | | | | instruction flag, and use the flag along with a virtual member function hook for targets to override if there are instructions that are only trivially rematerializable with specific operands (i.e. constant pool loads). llvm-svn: 37728
* Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoadDan Gohman2007-06-191-0/+14
| | | | | | | | | | with a general target hook to identify rematerializable instructions. Some instructions are only rematerializable with specific operands, such as loads from constant pools, while others are always rematerializable. This hook allows both to be identified as being rematerializable with the same mechanism. llvm-svn: 37644
* Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.Evan Cheng2007-06-191-29/+0
| | | | llvm-svn: 37643
* Instructions with unique labels or embedded jumptables cannot be duplicated ↵Evan Cheng2007-06-151-0/+29
| | | | | | during ifcvt. llvm-svn: 37606
* Handle blocks with 2 unconditional branches in AnalyzeBranch.Dale Johannesen2007-06-131-0/+10
| | | | llvm-svn: 37571
* Add a utility routine to check for unpredicated terminator instruction.Evan Cheng2007-06-081-3/+3
| | | | llvm-svn: 37528
* Fix ARM condition code subsumission check.Evan Cheng2007-06-081-3/+3
| | | | llvm-svn: 37517
* Stupid cut-n-paste bug caused me soooo much grief. Why wasn't there a ↵Evan Cheng2007-06-071-1/+1
| | | | | | compilation warning? I blame it on the FE folks. llvm-svn: 37484
* Add missing const qualifiers.Evan Cheng2007-05-291-9/+11
| | | | llvm-svn: 37342
* Hooks for predication support.Evan Cheng2007-05-231-8/+33
| | | | llvm-svn: 37308
* Fix some -march=thumb regressions. tBR_JTr is not predicable.Evan Cheng2007-05-211-1/+3
| | | | llvm-svn: 37272
* BlockHasNoFallThrough() now returns true if block ends with a return ↵Evan Cheng2007-05-211-2/+13
| | | | | | instruction; AnalyzeBranch() should ignore predicated instructionsd. llvm-svn: 37268
* RemoveBranch() and InsertBranch() now returns number of instructions deleted ↵Evan Cheng2007-05-181-7/+9
| | | | | | / inserted. llvm-svn: 37193
* PredicateInstruction returns true if the operation was successful.Evan Cheng2007-05-161-3/+7
| | | | llvm-svn: 37124
* Removed isPredicable().Evan Cheng2007-05-161-9/+0
| | | | llvm-svn: 37119
* Hooks for predication support.Evan Cheng2007-05-161-0/+22
| | | | llvm-svn: 37093
* Add PredicateOperand to all ARM instructions that have the condition field.Evan Cheng2007-05-151-16/+21
| | | | llvm-svn: 37066
* Rewrite of Thumb constant islands handling (exact allowance for paddingDale Johannesen2007-04-291-3/+4
| | | | | | around islands and jump tables). llvm-svn: 36573
* Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion.Evan Cheng2007-04-261-1/+1
| | | | llvm-svn: 36483
* Relex assertions to account for additional implicit def / use operands.Evan Cheng2007-04-251-1/+1
| | | | llvm-svn: 36430
* Removed tabs everywhere except autogenerated & external files. Add makeAnton Korobeynikov2007-04-161-2/+2
| | | | | | target for tabs checking. llvm-svn: 36146
* Inverted logic.Evan Cheng2007-04-031-1/+1
| | | | llvm-svn: 35619
* findRegisterUseOperand() changed.Evan Cheng2007-03-261-2/+2
| | | | llvm-svn: 35366
* Fix naming inconsistencies.Evan Cheng2007-03-191-2/+2
| | | | llvm-svn: 35163
* Spill / restore should avoid modifying the condition register.Evan Cheng2007-02-071-2/+2
| | | | llvm-svn: 33971
* Copy and paste bug.Evan Cheng2007-01-301-1/+11
| | | | llvm-svn: 33658
* Misseed thumb jumptable branch.Evan Cheng2007-01-301-0/+1
| | | | llvm-svn: 33656
* Factor GetInstSize() out of constpool island pass.Evan Cheng2007-01-291-1/+70
| | | | llvm-svn: 33644
* Make LABEL a builtin opcode.Jim Laskey2007-01-261-4/+0
| | | | llvm-svn: 33537
* ARM backend contribution from Apple.Evan Cheng2007-01-191-21/+384
| | | | llvm-svn: 33353
* Change MachineInstr ctor's to take a TargetInstrDescriptor reference insteadEvan Cheng2006-11-271-2/+3
| | | | | | of opcode and number of operands. llvm-svn: 31947
* fix warning about missing newline at end of fileRafael Espindola2006-10-241-1/+1
| | | | llvm-svn: 31162
* implement uncond branch insertion, mark branches with isBranch.Chris Lattner2006-10-241-0/+8
| | | | llvm-svn: 31160
* add shifts to addressing mode 1Rafael Espindola2006-09-131-3/+6
| | | | llvm-svn: 30291
* partial implementation of the ARM Addressing Mode 1Rafael Espindola2006-09-111-7/+7
| | | | llvm-svn: 30252
* change the addressing mode of the str instruction to reg+immRafael Espindola2006-08-081-0/+4
| | | | llvm-svn: 29571
* create the raddr addressing mode that matches any register and the frame indexRafael Espindola2006-07-101-22/+0
| | | | | | | | | use raddr for the ldr instruction. This removes a dummy mov from the assembly output remove SelectFrameIndex remove isLoadFromStackSlot remove isStoreToStackSlot llvm-svn: 29079
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