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authorEvan Cheng <evan.cheng@apple.com>2007-05-16 02:01:49 +0000
committerEvan Cheng <evan.cheng@apple.com>2007-05-16 02:01:49 +0000
commitad3aac71ce8fe6a94327e9ce620478cc51fff952 (patch)
treeedf147643332775c15dd4b2b43bfab23caa9fbbb /llvm/lib/Target/ARM/ARMInstrInfo.cpp
parentf5e53a58db3f9ddb1087c6d3a8ac3af1977df483 (diff)
downloadbcm5719-llvm-ad3aac71ce8fe6a94327e9ce620478cc51fff952.tar.gz
bcm5719-llvm-ad3aac71ce8fe6a94327e9ce620478cc51fff952.zip
Hooks for predication support.
llvm-svn: 37093
Diffstat (limited to 'llvm/lib/Target/ARM/ARMInstrInfo.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMInstrInfo.cpp22
1 files changed, 22 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
index 3f501a68ae1..de9ea48b265 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
@@ -423,6 +423,28 @@ ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
return false;
}
+bool ARMInstrInfo::isPredicatable(MachineInstr *MI) const {
+ const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+ if (TID->Flags & M_PREDICATED)
+ return true;
+
+ unsigned Opc = MI->getOpcode();
+ return Opc == ARM::B || Opc == ARM::tB;
+}
+
+void ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
+ std::vector<MachineOperand> &Cond) const {
+ unsigned Opc = MI->getOpcode();
+ if (Opc == ARM::B || Opc == ARM::tB) {
+ MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
+ MI->addImmOperand(Cond[0].getImmedValue());
+ return;
+ }
+
+ MachineOperand *PMO = MI->findFirstPredOperand();
+ PMO->setImm(Cond[0].getImmedValue());
+}
+
/// FIXME: Works around a gcc miscompilation with -fstrict-aliasing
static unsigned getNumJTEntries(const std::vector<MachineJumpTableEntry> &JT,
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