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| author | Evan Cheng <evan.cheng@apple.com> | 2007-02-07 00:06:56 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2007-02-07 00:06:56 +0000 |
| commit | ec13f826a2b87473146d340fa2443ebad456bae5 (patch) | |
| tree | e1129a3e40b40fd7140acf80d0dd173f825ca255 /llvm/lib/Target/ARM/ARMInstrInfo.cpp | |
| parent | dc0a9a7b4aaa5d8eb16f6068657bfa89a2f9a97c (diff) | |
| download | bcm5719-llvm-ec13f826a2b87473146d340fa2443ebad456bae5.tar.gz bcm5719-llvm-ec13f826a2b87473146d340fa2443ebad456bae5.zip | |
Spill / restore should avoid modifying the condition register.
llvm-svn: 33971
Diffstat (limited to 'llvm/lib/Target/ARM/ARMInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp b/llvm/lib/Target/ARM/ARMInstrInfo.cpp index 6adf645e493..36ed76d9616 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp @@ -83,7 +83,7 @@ unsigned ARMInstrInfo::isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) co return MI->getOperand(0).getReg(); } break; - case ARM::tLDRspi: + case ARM::tRestore: if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() && MI->getOperand(2).getImmedValue() == 0) { @@ -117,7 +117,7 @@ unsigned ARMInstrInfo::isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) con return MI->getOperand(0).getReg(); } break; - case ARM::tSTRspi: + case ARM::tSpill: if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() && MI->getOperand(2).getImmedValue() == 0) { |
