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| author | Rafael Espindola <rafael.espindola@gmail.com> | 2006-09-13 12:09:43 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2006-09-13 12:09:43 +0000 |
| commit | 3130a756ef5e6c43e8a25cf47a26fb803d442756 (patch) | |
| tree | 8bcb4a5d81c170c1578c862a94c18ac0798617fc /llvm/lib/Target/ARM/ARMInstrInfo.cpp | |
| parent | 84cc1f7cb8c66bd303dd1bac9899a24e02ac0d49 (diff) | |
| download | bcm5719-llvm-3130a756ef5e6c43e8a25cf47a26fb803d442756.tar.gz bcm5719-llvm-3130a756ef5e6c43e8a25cf47a26fb803d442756.zip | |
add shifts to addressing mode 1
llvm-svn: 30291
Diffstat (limited to 'llvm/lib/Target/ARM/ARMInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrInfo.cpp | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp b/llvm/lib/Target/ARM/ARMInstrInfo.cpp index da1479c8e53..810c254f9c0 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp @@ -33,15 +33,18 @@ bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg) const { MachineOpCode oc = MI.getOpcode(); switch (oc) { - case ARM::MOV: - assert(MI.getNumOperands() == 2 && + case ARM::MOV: { + assert(MI.getNumOperands() == 4 && MI.getOperand(0).isRegister() && "Invalid ARM MOV instruction"); - if (MI.getOperand(1).isRegister()) { + const MachineOperand &Arg = MI.getOperand(1); + const MachineOperand &Shift = MI.getOperand(2); + if (Arg.isRegister() && Shift.isImmediate() && Shift.getImmedValue() == 0) { SrcReg = MI.getOperand(1).getReg(); DstReg = MI.getOperand(0).getReg(); return true; } } + } return false; } |
